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Remove more ref patterns from the compiler #104721

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merged 3 commits into from
Nov 23, 2022
Merged

Remove more ref patterns from the compiler #104721

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616df0f
`rustc_parse`: remove `ref` patterns
WaffleLapkin Nov 22, 2022
a603635
`rustc_arena`: remove a couple of `ref` patterns
WaffleLapkin Nov 22, 2022
b97ec39
`rustc_ast_lowering`: remove `ref` patterns
WaffleLapkin Nov 22, 2022
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16 changes: 6 additions & 10 deletions compiler/rustc_arena/src/tests.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -52,19 +52,15 @@ fn test_arena_alloc_nested() {

impl<'a> Wrap<'a> {
fn alloc_inner<F: Fn() -> Inner>(&self, f: F) -> &Inner {
let r: &EI<'_> = self.0.alloc(EI::I(f()));
if let &EI::I(ref i) = r {
i
} else {
panic!("mismatch");
match self.0.alloc(EI::I(f())) {
EI::I(i) => i,
_ => panic!("mismatch"),
}
}
fn alloc_outer<F: Fn() -> Outer<'a>>(&self, f: F) -> &Outer<'_> {
let r: &EI<'_> = self.0.alloc(EI::O(f()));
if let &EI::O(ref o) = r {
o
} else {
panic!("mismatch");
match self.0.alloc(EI::O(f())) {
EI::O(o) => o,
_ => panic!("mismatch"),
}
}
}
Expand Down
32 changes: 15 additions & 17 deletions compiler/rustc_ast_lowering/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
.operands
.iter()
.map(|(op, op_sp)| {
let lower_reg = |reg| match reg {
let lower_reg = |&reg: &_| match reg {
InlineAsmRegOrRegClass::Reg(reg) => {
asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
asm::InlineAsmReg::parse(asm_arch, reg).unwrap_or_else(|error| {
Expand Down Expand Up @@ -152,32 +152,30 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
}
};

let op = match *op {
InlineAsmOperand::In { reg, ref expr } => hir::InlineAsmOperand::In {
let op = match op {
InlineAsmOperand::In { reg, expr } => hir::InlineAsmOperand::In {
reg: lower_reg(reg),
expr: self.lower_expr(expr),
},
InlineAsmOperand::Out { reg, late, ref expr } => hir::InlineAsmOperand::Out {
InlineAsmOperand::Out { reg, late, expr } => hir::InlineAsmOperand::Out {
reg: lower_reg(reg),
late,
late: *late,
expr: expr.as_ref().map(|expr| self.lower_expr(expr)),
},
InlineAsmOperand::InOut { reg, late, ref expr } => {
hir::InlineAsmOperand::InOut {
reg: lower_reg(reg),
late,
expr: self.lower_expr(expr),
}
}
InlineAsmOperand::SplitInOut { reg, late, ref in_expr, ref out_expr } => {
InlineAsmOperand::InOut { reg, late, expr } => hir::InlineAsmOperand::InOut {
reg: lower_reg(reg),
late: *late,
expr: self.lower_expr(expr),
},
InlineAsmOperand::SplitInOut { reg, late, in_expr, out_expr } => {
hir::InlineAsmOperand::SplitInOut {
reg: lower_reg(reg),
late,
late: *late,
in_expr: self.lower_expr(in_expr),
out_expr: out_expr.as_ref().map(|expr| self.lower_expr(expr)),
}
}
InlineAsmOperand::Const { ref anon_const } => {
InlineAsmOperand::Const { anon_const } => {
if !self.tcx.features().asm_const {
feature_err(
&sess.parse_sess,
Expand All @@ -191,7 +189,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
anon_const: self.lower_anon_const(anon_const),
}
}
InlineAsmOperand::Sym { ref sym } => {
InlineAsmOperand::Sym { sym } => {
let static_def_id = self
.resolver
.get_partial_res(sym.id)
Expand Down Expand Up @@ -347,7 +345,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
skip = true;

let idx2 = *o.get();
let &(ref op2, op_sp2) = &operands[idx2];
let (ref op2, op_sp2) = operands[idx2];
let Some(asm::InlineAsmRegOrRegClass::Reg(reg2)) = op2.reg() else {
unreachable!();
};
Expand Down
10 changes: 5 additions & 5 deletions compiler/rustc_ast_lowering/src/block.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -31,16 +31,16 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
let mut stmts = SmallVec::<[hir::Stmt<'hir>; 8]>::new();
let mut expr = None;
while let [s, tail @ ..] = ast_stmts {
match s.kind {
StmtKind::Local(ref local) => {
match &s.kind {
StmtKind::Local(local) => {
let hir_id = self.lower_node_id(s.id);
let local = self.lower_local(local);
self.alias_attrs(hir_id, local.hir_id);
let kind = hir::StmtKind::Local(local);
let span = self.lower_span(s.span);
stmts.push(hir::Stmt { hir_id, kind, span });
}
StmtKind::Item(ref it) => {
StmtKind::Item(it) => {
stmts.extend(self.lower_item_ref(it).into_iter().enumerate().map(
|(i, item_id)| {
let hir_id = match i {
Expand All @@ -53,7 +53,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
},
));
}
StmtKind::Expr(ref e) => {
StmtKind::Expr(e) => {
let e = self.lower_expr(e);
if tail.is_empty() {
expr = Some(e);
Expand All @@ -65,7 +65,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
stmts.push(hir::Stmt { hir_id, kind, span });
}
}
StmtKind::Semi(ref e) => {
StmtKind::Semi(e) => {
let e = self.lower_expr(e);
let hir_id = self.lower_node_id(s.id);
self.alias_attrs(hir_id, e.hir_id);
Expand Down
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