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Merged
merged 4 commits into from
Dec 20, 2023
Merged

add more niches to rawvec #106790

merged 4 commits into from
Dec 20, 2023

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the8472
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@the8472 the8472 commented Jan 12, 2023

Previously RawVec only had a single niche in its NonNull pointer. With this change it now has isize::MAX niches since half the value-space of the capacity field is never needed, we can't have a capacity larger than isize::MAX.

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. labels Jan 12, 2023
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the8472 commented Jan 12, 2023

@bors try @rust-timer queue

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@rustbot rustbot added the S-waiting-on-perf Status: Waiting on a perf run to be completed. label Jan 12, 2023
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bors commented Jan 12, 2023

⌛ Trying commit 8931339c66517a0a483178d6df89dcace3319917 with merge 1ae3d03661895b5c5111a5301f838129f7d63279...

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bors commented Jan 13, 2023

☀️ Try build successful - checks-actions
Build commit: 1ae3d03661895b5c5111a5301f838129f7d63279 (1ae3d03661895b5c5111a5301f838129f7d63279)

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Finished benchmarking commit (1ae3d03661895b5c5111a5301f838129f7d63279): comparison URL.

Overall result: ❌✅ regressions and improvements - ACTION NEEDED

Benchmarking this pull request likely means that it is perf-sensitive, so we're automatically marking it as not fit for rolling up. While you can manually mark this PR as fit for rollup, we strongly recommend not doing so since this PR may lead to changes in compiler perf.

Next Steps: If you can justify the regressions found in this try perf run, please indicate this with @rustbot label: +perf-regression-triaged along with sufficient written justification. If you cannot justify the regressions please fix the regressions and do another perf run. If the next run shows neutral or positive results, the label will be automatically removed.

@bors rollup=never
@rustbot label: -S-waiting-on-perf +perf-regression

Instruction count

This is a highly reliable metric that was used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
0.4% [0.2%, 1.0%] 75
Regressions ❌
(secondary)
0.5% [0.2%, 1.8%] 57
Improvements ✅
(primary)
-0.7% [-1.0%, -0.5%] 4
Improvements ✅
(secondary)
-0.9% [-1.3%, -0.2%] 4
All ❌✅ (primary) 0.3% [-1.0%, 1.0%] 79

Max RSS (memory usage)

Results

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
3.7% [0.2%, 8.6%] 8
Regressions ❌
(secondary)
- - 0
Improvements ✅
(primary)
-1.9% [-3.3%, -0.6%] 2
Improvements ✅
(secondary)
-1.9% [-3.2%, -0.8%] 4
All ❌✅ (primary) 2.5% [-3.3%, 8.6%] 10

Cycles

This benchmark run did not return any relevant results for this metric.

@rustbot rustbot added perf-regression Performance regression. and removed S-waiting-on-perf Status: Waiting on a perf run to be completed. labels Jan 13, 2023
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@the8472 the8472 force-pushed the rawvec-niche branch 2 times, most recently from e66f83b to 3cdb30f Compare January 14, 2023 10:19
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the8472 commented Jan 14, 2023

@bors try @rust-timer queue

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@rustbot rustbot added the S-waiting-on-perf Status: Waiting on a perf run to be completed. label Jan 14, 2023
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bors commented Jan 14, 2023

⌛ Trying commit 3cdb30fbb40079772b66935005437f64a6f82cd6 with merge 1a6380e7ce4866ed5915d216afdc6890b8b11efa...

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bors commented Jan 14, 2023

☀️ Try build successful - checks-actions
Build commit: 1a6380e7ce4866ed5915d216afdc6890b8b11efa (1a6380e7ce4866ed5915d216afdc6890b8b11efa)

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Finished benchmarking commit (1a6380e7ce4866ed5915d216afdc6890b8b11efa): comparison URL.

Overall result: ❌✅ regressions and improvements - ACTION NEEDED

Benchmarking this pull request likely means that it is perf-sensitive, so we're automatically marking it as not fit for rolling up. While you can manually mark this PR as fit for rollup, we strongly recommend not doing so since this PR may lead to changes in compiler perf.

Next Steps: If you can justify the regressions found in this try perf run, please indicate this with @rustbot label: +perf-regression-triaged along with sufficient written justification. If you cannot justify the regressions please fix the regressions and do another perf run. If the next run shows neutral or positive results, the label will be automatically removed.

@bors rollup=never
@rustbot label: -S-waiting-on-perf +perf-regression

Instruction count

This is a highly reliable metric that was used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
0.4% [0.2%, 0.9%] 95
Regressions ❌
(secondary)
0.6% [0.3%, 1.7%] 49
Improvements ✅
(primary)
-0.6% [-0.9%, -0.3%] 3
Improvements ✅
(secondary)
-1.1% [-1.2%, -0.8%] 3
All ❌✅ (primary) 0.3% [-0.9%, 0.9%] 98

Max RSS (memory usage)

Results

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
3.9% [0.1%, 8.7%] 7
Regressions ❌
(secondary)
4.2% [4.2%, 4.2%] 1
Improvements ✅
(primary)
-1.9% [-2.6%, -1.2%] 2
Improvements ✅
(secondary)
-2.2% [-3.0%, -1.5%] 2
All ❌✅ (primary) 2.6% [-2.6%, 8.7%] 9

Cycles

Results

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
- - 0
Regressions ❌
(secondary)
- - 0
Improvements ✅
(primary)
- - 0
Improvements ✅
(secondary)
-2.0% [-2.0%, -2.0%] 1
All ❌✅ (primary) - - 0

@rustbot rustbot removed the S-waiting-on-perf Status: Waiting on a perf run to be completed. label Jan 14, 2023
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the8472 commented Jan 14, 2023

Besides the performance results adding the niche also regresses tests/codegen/issue-103840.rs (#103840). CC @nikic do you have any pointers?

IR on master:

; ModuleID = 'issue_103840.f9de1d84-cgu.0'
source_filename = "issue_103840.f9de1d84-cgu.0"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; issue_103840::foo
; Function Attrs: nonlazybind uwtable
define void @_ZN12issue_1038403foo17he2821c63cd4c4830E(ptr noalias nocapture noundef align 8 dereferenceable(24) %t) unnamed_addr #0 personality ptr @rust_eh_personality {
start:
  %taken.sroa.0 = alloca { i64, ptr }, align 8
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %taken.sroa.0)
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %taken.sroa.0, ptr noundef nonnull align 8 dereferenceable(16) %t, i64 16, i1 false), !alias.scope !2, !noalias !6
  %taken.sroa.4.0.t.sroa_idx = getelementptr inbounds i8, ptr %t, i64 16
  %taken.sroa.4.0.copyload3 = load i64, ptr %taken.sroa.4.0.t.sroa_idx, align 8, !alias.scope !2, !noalias !6
  %0 = icmp eq i64 %taken.sroa.4.0.copyload3, 0
  %1 = add i64 %taken.sroa.4.0.copyload3, -1
  %spec.select = select i1 %0, i64 0, i64 %1
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %t, ptr noundef nonnull align 8 dereferenceable(16) %taken.sroa.0, i64 16, i1 false)
  store i64 %spec.select, ptr %taken.sroa.4.0.t.sroa_idx, align 8
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %taken.sroa.0)
  ret void
}

; Function Attrs: nonlazybind uwtable
declare noundef i32 @rust_eh_personality(i32, i32 noundef, i64, ptr, ptr) unnamed_addr #0

; Function Attrs: argmemonly mustprogress nocallback nofree nounwind willreturn
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: argmemonly mustprogress nocallback nofree nosync nounwind willreturn
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: argmemonly mustprogress nocallback nofree nosync nounwind willreturn
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { nonlazybind uwtable "probe-stack"="__rust_probestack" "target-cpu"="x86-64" }
attributes #1 = { argmemonly mustprogress nocallback nofree nounwind willreturn }
attributes #2 = { argmemonly mustprogress nocallback nofree nosync nounwind willreturn }

!llvm.module.flags = !{!0, !1}

!0 = !{i32 7, !"PIC Level", i32 2}
!1 = !{i32 2, !"RtLibUseGOT", i32 1}
!2 = !{!3, !5}
!3 = distinct !{!3, !4, !"_ZN4core3mem7replace17h94c060526cb48374E: %result"}
!4 = distinct !{!4, !"_ZN4core3mem7replace17h94c060526cb48374E"}
!5 = distinct !{!5, !4, !"_ZN4core3mem7replace17h94c060526cb48374E: %dest"}
!6 = !{!7}
!7 = distinct !{!7, !4, !"_ZN4core3mem7replace17h94c060526cb48374E: %src"}

this PR:

; ModuleID = 'issue_103840.f9de1d84-cgu.0'
source_filename = "issue_103840.f9de1d84-cgu.0"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; issue_103840::foo
; Function Attrs: nonlazybind uwtable
define void @_ZN12issue_1038403foo17he2821c63cd4c4830E(ptr noalias nocapture noundef align 8 dereferenceable(24) %t) unnamed_addr #0 personality ptr @rust_eh_personality {
start:
  %taken.sroa.0 = alloca { ptr, i64 }, align 8
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %taken.sroa.0)
  tail call void @llvm.experimental.noalias.scope.decl(metadata !2)
  tail call void @llvm.experimental.noalias.scope.decl(metadata !5)
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %taken.sroa.0, ptr noundef nonnull align 8 dereferenceable(16) %t, i64 16, i1 false), !alias.scope !7, !noalias !5
  %taken.sroa.4.0.t.sroa_idx = getelementptr inbounds i8, ptr %t, i64 16
  %taken.sroa.4.0.copyload3 = load i64, ptr %taken.sroa.4.0.t.sroa_idx, align 8, !alias.scope !7, !noalias !5
  store ptr inttoptr (i64 8 to ptr), ptr %t, align 8, !alias.scope !9, !noalias !2
  %_9.sroa.4.0.t.sroa_idx = getelementptr inbounds i8, ptr %t, i64 8
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %_9.sroa.4.0.t.sroa_idx, i8 0, i64 16, i1 false)
  tail call void @llvm.experimental.noalias.scope.decl(metadata !10)
  %_4.i.i.i.i = load i64, ptr %_9.sroa.4.0.t.sroa_idx, align 8, !alias.scope !13, !noalias !16
  %_3.i.i.i.i = icmp eq i64 %_4.i.i.i.i, 0
  br i1 %_3.i.i.i.i, label %bb4, label %bb2.i.i.i

bb2.i.i.i:                                        ; preds = %start
  %_6.i.i.i.i.i = icmp ult i64 %_4.i.i.i.i, 1152921504606846976
  %array_size.i.i.i.i.i = shl nuw nsw i64 %_4.i.i.i.i, 3
  tail call void @llvm.assume(i1 %_6.i.i.i.i.i)
  tail call void @__rust_dealloc(ptr nonnull inttoptr (i64 8 to ptr), i64 %array_size.i.i.i.i.i, i64 8) #7, !noalias !10
  br label %bb4

bb4:                                              ; preds = %bb2.i.i.i, %start
  %0 = icmp eq i64 %taken.sroa.4.0.copyload3, 0
  %1 = add i64 %taken.sroa.4.0.copyload3, -1
  %spec.select = select i1 %0, i64 0, i64 %1
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %t, ptr noundef nonnull align 8 dereferenceable(16) %taken.sroa.0, i64 16, i1 false)
  store i64 %spec.select, ptr %taken.sroa.4.0.t.sroa_idx, align 8
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %taken.sroa.0)
  ret void
}

; Function Attrs: nonlazybind uwtable
declare noundef i32 @rust_eh_personality(i32, i32 noundef, i64, ptr, ptr) unnamed_addr #0

; Function Attrs: argmemonly mustprogress nocallback nofree nounwind willreturn
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: inaccessiblememonly mustprogress nocallback nofree nosync nounwind willreturn
declare void @llvm.assume(i1 noundef) #2

; Function Attrs: nounwind nonlazybind allockind("free") uwtable
declare void @__rust_dealloc(ptr allocptr, i64, i64) unnamed_addr #3

; Function Attrs: argmemonly mustprogress nocallback nofree nosync nounwind willreturn
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: argmemonly mustprogress nocallback nofree nosync nounwind willreturn
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: argmemonly nocallback nofree nounwind willreturn writeonly
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #5

; Function Attrs: inaccessiblememonly nocallback nofree nosync nounwind willreturn
declare void @llvm.experimental.noalias.scope.decl(metadata) #6

attributes #0 = { nonlazybind uwtable "probe-stack"="__rust_probestack" "target-cpu"="x86-64" }
attributes #1 = { argmemonly mustprogress nocallback nofree nounwind willreturn }
attributes #2 = { inaccessiblememonly mustprogress nocallback nofree nosync nounwind willreturn }
attributes #3 = { nounwind nonlazybind allockind("free") uwtable "alloc-family"="__rust_alloc" "probe-stack"="__rust_probestack" "target-cpu"="x86-64" }
attributes #4 = { argmemonly mustprogress nocallback nofree nosync nounwind willreturn }
attributes #5 = { argmemonly nocallback nofree nounwind willreturn writeonly }
attributes #6 = { inaccessiblememonly nocallback nofree nosync nounwind willreturn }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1}

!0 = !{i32 7, !"PIC Level", i32 2}
!1 = !{i32 2, !"RtLibUseGOT", i32 1}
!2 = !{!3}
!3 = distinct !{!3, !4, !"_ZN4core3mem7replace17h94c060526cb48374E: %result"}
!4 = distinct !{!4, !"_ZN4core3mem7replace17h94c060526cb48374E"}
!5 = !{!6}
!6 = distinct !{!6, !4, !"_ZN4core3mem7replace17h94c060526cb48374E: %src"}
!7 = !{!3, !8}
!8 = distinct !{!8, !4, !"_ZN4core3mem7replace17h94c060526cb48374E: %dest"}
!9 = !{!8, !6}
!10 = !{!11}
!11 = distinct !{!11, !12, !"_ZN77_$LT$alloc..raw_vec..RawVec$LT$T$C$A$GT$$u20$as$u20$core..ops..drop..Drop$GT$4drop17he64f84a0747c6173E: %self"}
!12 = distinct !{!12, !"_ZN77_$LT$alloc..raw_vec..RawVec$LT$T$C$A$GT$$u20$as$u20$core..ops..drop..Drop$GT$4drop17he64f84a0747c6173E"}
!13 = !{!14, !11}
!14 = distinct !{!14, !15, !"_ZN5alloc7raw_vec19RawVec$LT$T$C$A$GT$14current_memory17hcd327976cb9281f7E: %self"}
!15 = distinct !{!15, !"_ZN5alloc7raw_vec19RawVec$LT$T$C$A$GT$14current_memory17hcd327976cb9281f7E"}
!16 = !{!17}
!17 = distinct !{!17, !15, !"_ZN5alloc7raw_vec19RawVec$LT$T$C$A$GT$14current_memory17hcd327976cb9281f7E: argument 0"}

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nikic commented Jan 14, 2023

@the8472 Looks like it reverted to the previous state, so that should get fixed by the next LLVM upgrade.

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the8472 commented Jan 14, 2023

Ok, then I'll wait for that. Maybe my distro's valgrind will be updated by then too.

@the8472 the8472 added the S-blocked Status: Blocked on something else such as an RFC or other implementation work. label Jan 14, 2023
@bors bors added S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. and removed S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. labels Dec 11, 2023
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the8472 commented Dec 11, 2023

@bors r=scottmcm

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bors commented Dec 11, 2023

📌 Commit 8199709 has been approved by scottmcm

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. labels Dec 11, 2023
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bors commented Dec 12, 2023

⌛ Testing commit 8199709 with merge be177d0...

bors added a commit to rust-lang-ci/rust that referenced this pull request Dec 12, 2023
add more niches to rawvec

Previously RawVec only had a single niche in its `NonNull` pointer. With this change it now has `isize::MAX` niches since half the value-space of the capacity field is never needed, we can't have a capacity larger than isize::MAX.
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bors commented Dec 12, 2023

💔 Test failed - checks-actions

@bors bors added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. labels Dec 12, 2023
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the8472 commented Dec 19, 2023

@bors r=scottmcm

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bors commented Dec 19, 2023

📌 Commit f6150db has been approved by scottmcm

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Dec 19, 2023
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bors commented Dec 20, 2023

⌛ Testing commit f6150db with merge 51c0db6...

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bors commented Dec 20, 2023

☀️ Test successful - checks-actions
Approved by: scottmcm
Pushing 51c0db6 to master...

@bors bors added the merged-by-bors This PR was explicitly merged by bors. label Dec 20, 2023
@bors bors merged commit 51c0db6 into rust-lang:master Dec 20, 2023
@rustbot rustbot added this to the 1.76.0 milestone Dec 20, 2023
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Finished benchmarking commit (51c0db6): comparison URL.

Overall result: ❌✅ regressions and improvements - ACTION NEEDED

Next Steps: If you can justify the regressions found in this perf run, please indicate this with @rustbot label: +perf-regression-triaged along with sufficient written justification. If you cannot justify the regressions please open an issue or create a new PR that fixes the regressions, add a comment linking to the newly created issue or PR, and then add the perf-regression-triaged label to this PR.

@rustbot label: +perf-regression
cc @rust-lang/wg-compiler-performance

Instruction count

This is a highly reliable metric that was used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
0.4% [0.1%, 0.7%] 20
Regressions ❌
(secondary)
0.6% [0.2%, 1.0%] 2
Improvements ✅
(primary)
-0.4% [-2.0%, -0.1%] 27
Improvements ✅
(secondary)
-0.9% [-5.3%, -0.2%] 16
All ❌✅ (primary) -0.1% [-2.0%, 0.7%] 47

Max RSS (memory usage)

Results

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
2.2% [0.7%, 5.9%] 6
Regressions ❌
(secondary)
5.4% [2.0%, 10.4%] 9
Improvements ✅
(primary)
-3.5% [-16.2%, -0.2%] 15
Improvements ✅
(secondary)
-3.4% [-4.8%, -2.0%] 5
All ❌✅ (primary) -1.9% [-16.2%, 5.9%] 21

Cycles

Results

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
0.6% [0.4%, 0.8%] 2
Regressions ❌
(secondary)
2.0% [1.3%, 2.5%] 5
Improvements ✅
(primary)
-1.6% [-1.6%, -1.6%] 1
Improvements ✅
(secondary)
-2.6% [-3.8%, -1.4%] 2
All ❌✅ (primary) -0.1% [-1.6%, 0.8%] 3

Binary size

Results

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

mean range count
Regressions ❌
(primary)
0.2% [0.0%, 0.7%] 56
Regressions ❌
(secondary)
0.6% [0.0%, 1.1%] 6
Improvements ✅
(primary)
-0.2% [-0.4%, -0.0%] 9
Improvements ✅
(secondary)
- - 0
All ❌✅ (primary) 0.1% [-0.4%, 0.7%] 65

Bootstrap: 674.398s -> 675.418s (0.15%)
Artifact size: 312.41 MiB -> 312.80 MiB (0.12%)

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Small but widespread binary size regressions here, which the pre-merge runs also showed :/

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Kobzol commented Dec 26, 2023

It's clear that this PR affected a lot of LLVM inlining/optimization decisions, which also in turn affected binary size. I'm not sure if we can do a lot with that, as long as we deem that the added niche is a good idea.

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merged-by-bors This PR was explicitly merged by bors. perf-regression Performance regression. S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue.
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