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Add no_std Xtensa targets support #125141
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c72fcfb
Add Xtensa as an experimental target
MabezDev b37a448
Teach rustc about the Xtensa arch.
MabezDev e823288
Teach rustc about the Xtensa call ABI.
MabezDev 11f70d7
Add no_std Xtensa targets support
SergioGasquez 9e58c5e
Update download-ci-llvm-stamp
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@@ -23,6 +23,7 @@ const OPTIONAL_COMPONENTS: &[&str] = &[ | |
"nvptx", | ||
"hexagon", | ||
"riscv", | ||
"xtensa", | ||
"bpf", | ||
]; | ||
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|
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@@ -0,0 +1,123 @@ | ||
//! The Xtensa ABI implementation | ||
//! | ||
//! This ABI implementation is based on the following sources: | ||
//! | ||
//! Section 8.1.4 & 8.1.5 of the Xtensa ISA reference manual, as well as snippets from | ||
//! Section 2.3 from the Xtensa programmers guide. | ||
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use crate::abi::call::{ArgAbi, FnAbi, Reg, Uniform}; | ||
use crate::abi::{Abi, HasDataLayout, Size, TyAbiInterface}; | ||
use crate::spec::HasTargetSpec; | ||
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const NUM_ARG_GPRS: u64 = 6; | ||
const NUM_RET_GPRS: u64 = 4; | ||
const MAX_ARG_IN_REGS_SIZE: u64 = NUM_ARG_GPRS * 32; | ||
const MAX_RET_IN_REGS_SIZE: u64 = NUM_RET_GPRS * 32; | ||
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fn classify_ret_ty<'a, Ty, C>(arg: &mut ArgAbi<'_, Ty>) | ||
where | ||
Ty: TyAbiInterface<'a, C> + Copy, | ||
{ | ||
if arg.is_ignore() { | ||
return; | ||
} | ||
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// The rules for return and argument types are the same, | ||
// so defer to `classify_arg_ty`. | ||
let mut arg_gprs_left = NUM_RET_GPRS; | ||
classify_arg_ty(arg, &mut arg_gprs_left, MAX_RET_IN_REGS_SIZE); | ||
// Ret args cannot be passed via stack, we lower to indirect and let the backend handle the invisble reference | ||
match arg.mode { | ||
super::PassMode::Indirect { attrs: _, meta_attrs: _, ref mut on_stack } => { | ||
*on_stack = false; | ||
} | ||
_ => {} | ||
} | ||
} | ||
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fn classify_arg_ty<'a, Ty, C>(arg: &mut ArgAbi<'_, Ty>, arg_gprs_left: &mut u64, max_size: u64) | ||
where | ||
Ty: TyAbiInterface<'a, C> + Copy, | ||
{ | ||
assert!(*arg_gprs_left <= NUM_ARG_GPRS, "Arg GPR tracking underflow"); | ||
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// Ignore empty structs/unions. | ||
if arg.layout.is_zst() { | ||
return; | ||
} | ||
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let size = arg.layout.size.bits(); | ||
let needed_align = arg.layout.align.abi.bits(); | ||
let mut must_use_stack = false; | ||
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// Determine the number of GPRs needed to pass the current argument | ||
// according to the ABI. 2*XLen-aligned varargs are passed in "aligned" | ||
// register pairs, so may consume 3 registers. | ||
let mut needed_arg_gprs = (size + 32 - 1) / 32; | ||
if needed_align == 64 { | ||
needed_arg_gprs += *arg_gprs_left % 2; | ||
} | ||
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if needed_arg_gprs > *arg_gprs_left | ||
|| needed_align > 128 | ||
|| (*arg_gprs_left < (max_size / 32) && needed_align == 128) | ||
{ | ||
must_use_stack = true; | ||
needed_arg_gprs = *arg_gprs_left; | ||
} | ||
*arg_gprs_left -= needed_arg_gprs; | ||
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if must_use_stack { | ||
arg.make_indirect_byval(None); | ||
} else { | ||
if is_xtensa_aggregate(arg) { | ||
// Aggregates which are <= max_size will be passed in | ||
// registers if possible, so coerce to integers. | ||
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// Use a single `xlen` int if possible, 2 * `xlen` if 2 * `xlen` alignment | ||
// is required, and a 2-element `xlen` array if only `xlen` alignment is | ||
// required. | ||
if size <= 32 { | ||
arg.cast_to(Reg::i32()); | ||
} else { | ||
let reg = if needed_align == 2 * 32 { Reg::i64() } else { Reg::i32() }; | ||
let total = Size::from_bits(((size + 32 - 1) / 32) * 32); | ||
arg.cast_to(Uniform::new(reg, total)); | ||
} | ||
} else { | ||
// All integral types are promoted to `xlen` | ||
// width. | ||
// | ||
// We let the LLVM backend handle integral types >= xlen. | ||
if size < 32 { | ||
arg.extend_integer_width_to(32); | ||
} | ||
} | ||
} | ||
} | ||
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pub fn compute_abi_info<'a, Ty, C>(_cx: &C, fn_abi: &mut FnAbi<'a, Ty>) | ||
where | ||
Ty: TyAbiInterface<'a, C> + Copy, | ||
C: HasDataLayout + HasTargetSpec, | ||
{ | ||
if !fn_abi.ret.is_ignore() { | ||
classify_ret_ty(&mut fn_abi.ret); | ||
} | ||
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let mut arg_gprs_left = NUM_ARG_GPRS; | ||
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for arg in fn_abi.args.iter_mut() { | ||
if arg.is_ignore() { | ||
continue; | ||
} | ||
classify_arg_ty(arg, &mut arg_gprs_left, MAX_ARG_IN_REGS_SIZE); | ||
} | ||
} | ||
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fn is_xtensa_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool { | ||
match arg.layout.abi { | ||
Abi::Vector { .. } => true, | ||
_ => arg.layout.is_aggregate(), | ||
} | ||
} |
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@@ -0,0 +1,17 @@ | ||
use crate::abi::Endian; | ||
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, TargetOptions}; | ||
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pub fn opts() -> TargetOptions { | ||
TargetOptions { | ||
os: "none".into(), | ||
endian: Endian::Little, | ||
c_int_width: "32".into(), | ||
linker_flavor: LinkerFlavor::Gnu(Cc::Yes, Lld::No), | ||
executables: true, | ||
panic_strategy: PanicStrategy::Abort, | ||
relocation_model: RelocModel::Static, | ||
emit_debug_gdb_scripts: false, | ||
atomic_cas: false, | ||
..Default::default() | ||
} | ||
} |
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24 changes: 24 additions & 0 deletions
24
compiler/rustc_target/src/spec/targets/xtensa_esp32_none_elf.rs
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use crate::spec::{base::xtensa, Target, TargetOptions}; | ||
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pub fn target() -> Target { | ||
Target { | ||
llvm_target: "xtensa-none-elf".into(), | ||
pointer_width: 32, | ||
data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(), | ||
arch: "xtensa".into(), | ||
metadata: crate::spec::TargetMetadata { | ||
description: Some("Xtensa ESP32".into()), | ||
tier: Some(3), | ||
host_tools: Some(false), | ||
std: Some(false), | ||
}, | ||
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options: TargetOptions { | ||
cpu: "esp32".into(), | ||
linker: Some("xtensa-esp32-elf-gcc".into()), | ||
max_atomic_width: Some(32), | ||
atomic_cas: true, | ||
..xtensa::opts() | ||
}, | ||
} | ||
} |
23 changes: 23 additions & 0 deletions
23
compiler/rustc_target/src/spec/targets/xtensa_esp32s2_none_elf.rs
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use crate::spec::{base::xtensa, Target, TargetOptions}; | ||
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pub fn target() -> Target { | ||
Target { | ||
llvm_target: "xtensa-none-elf".into(), | ||
pointer_width: 32, | ||
data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(), | ||
arch: "xtensa".into(), | ||
metadata: crate::spec::TargetMetadata { | ||
description: Some("Xtensa ESP32-S2".into()), | ||
tier: Some(3), | ||
host_tools: Some(false), | ||
std: Some(false), | ||
}, | ||
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options: TargetOptions { | ||
cpu: "esp32-s2".into(), | ||
linker: Some("xtensa-esp32s2-elf-gcc".into()), | ||
max_atomic_width: Some(32), | ||
..xtensa::opts() | ||
}, | ||
} | ||
} |
24 changes: 24 additions & 0 deletions
24
compiler/rustc_target/src/spec/targets/xtensa_esp32s3_none_elf.rs
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@@ -0,0 +1,24 @@ | ||
use crate::spec::{base::xtensa, Target, TargetOptions}; | ||
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pub fn target() -> Target { | ||
Target { | ||
llvm_target: "xtensa-none-elf".into(), | ||
pointer_width: 32, | ||
data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(), | ||
arch: "xtensa".into(), | ||
metadata: crate::spec::TargetMetadata { | ||
description: Some("Xtensa ESP32-S3".into()), | ||
tier: Some(3), | ||
host_tools: Some(false), | ||
std: Some(false), | ||
}, | ||
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options: TargetOptions { | ||
cpu: "esp32-s3".into(), | ||
linker: Some("xtensa-esp32s3-elf-gcc".into()), | ||
max_atomic_width: Some(32), | ||
atomic_cas: true, | ||
..xtensa::opts() | ||
}, | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -1,4 +1,4 @@ | ||
Change this file to make users of the `download-ci-llvm` configuration download | ||
a new version of LLVM from CI, even if the LLVM submodule hasn’t changed. | ||
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Last change is for: https://github.com/rust-lang/rust/pull/120761 | ||
Last change is for: https://github.com/rust-lang/rust/pull/125141 |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,25 @@ | ||
# `xtensa-*` | ||
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**Tier: 3** | ||
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Targets for Xtensa CPUs. | ||
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## Target maintainers | ||
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- Scott Mabin [@MabezDev](https://github.com/MabezDev) | ||
- Sergio Gasquez [@SergioGasquez](https://github.com/SergioGasquez) | ||
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## Requirements | ||
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The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined: | ||
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| Target name | Target CPU(s) | | ||
| ------------------------- | --------------------------------------------------------------- | | ||
| `xtensa-esp32-none-elf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) | | ||
| `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) | | ||
| `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) | | ||
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## Building the target | ||
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The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of the The Rust on ESP Book](https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html). |
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This seem to be wrong? I got the following error when building for this target:
https://github.com/taiki-e/portable-atomic/actions/runs/9492602960/job/26160155007#step:6:1583
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Rust is not currently using a new enough LLVM to include the patches to generate code (discussed here: #125141 (comment)), so for now, you still need the esp toolchain in your CI. I think by switching to LLVM 18, or latest LLVM 19 we should be able to build some basic binaries.