Code

Add RISC-V vxworks targets#130549

Code

Merged

bors merged 4 commits intorust-lang:masterrust-lang/rust:masterfrom biabbas:riscv32_wrs_vxworksbiabbas/rustLangRust:riscv32_wrs_vxworksCopy head branch name to clipboardSep 25, 2024

+66-5

Commits

Commits on Sep 20, 2024

• Add Vxworks RISC-V targets

  biabbas

  committed
  485e90f

  Copy full SHA for 485e90f

• Update std support for all vxworks target archs

  biabbas

  committed
  eb6a52c

  Copy full SHA for eb6a52c

• Allow unused unsafe for vxworks in alligned_malloc to resolve build errors

  biabbas

  committed
  4957eda

  Copy full SHA for 4957eda

Commits on Sep 25, 2024

• Vxworks riscv target specs: remove redundant zicsr feature

  biabbas

  committed
  6d229f8

  Copy full SHA for 6d229f8