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callconv: adapt mips padding logic to mips64 #148294

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callconv: adapt mips padding logic to mips64 #148294

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@chenx97 chenx97 commented Oct 30, 2025

Similar to mips, mips64 also adds a padding register when an aggregate argument is not passed with an aligned offset, for any byte alignment a where 8 < a <= 16 bytes.

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Oct 30, 2025
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r? @petrochenkov

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@chenx97 chenx97 marked this pull request as draft October 31, 2025 11:47
@rustbot rustbot added S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Oct 31, 2025
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callconv: adapt mips padding logic to mips64
2b8161f 
Similar to mips, mips64 also adds a padding register when an aggregate
argument is not passed with an aligned offset, for any byte alignment `a`
where `8 < a <= 16` bytes.

This fix uses an i32 padding, but it should work just fine because i32 is
aligned like i64 for arguments.
@chenx97 chenx97 force-pushed the mips64-padding-aggregate-args branch from fa68eff to 2b8161f Compare November 2, 2025 16:34
@chenx97 chenx97 marked this pull request as ready for review November 2, 2025 16:35
@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. labels Nov 2, 2025
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chenx97 commented Nov 4, 2025

r? @workingjubilee

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