add test for codegen of SIMD vector from array repeat

[folkertdev]

fixes #97804

It appears that this issue was fixed silently in LLVM 19. The original codegen was terrible, but starting at LLVM 19 opt is able to generate good code.

https://llvm.godbolt.org/z/5vq8scP6q

cc @programmerjake

[rustbot]

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[folkertdev]

Hmm, it is fixed on x86_64 and aarch64, but not for other targets where vector types require a target feature.

• for s390x it only optimizes when the vector target feature is available
• for wasm32 even with +simd128 it does not optimize (should just be a splat I think?)

Do we consider that fixed?

[folkertdev]

I did file llvm/llvm-project#178940 for the wasm issue, cc @nikic

[workingjubilee]

For s390x without +vector, it probably comes from type legalization: LLVM, if it can't fit a type or operation with that type to a series of machine operations, will, during... lowering to SelectionDAG, I think?... "scalarize" the operations into operations on a valid type.

[folkertdev]

I'm a bit out of my depth here, but I would expect the transformation to a vector splat to happen much earlier than that. You're right that it does appear use information about what types are legal for the current target though.

[workingjubilee]

I think this is fine to merge if the test gets qualified with the appropriate architectures or whatever.

[Mark-Simulacrum]

@rustbot author

Yeah, with appropriate ignore-X added seems OK to approve, though we should probably leave the issue open in that case?

[rustbot]

Reminder, once the PR becomes ready for a review, use @rustbot ready.