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f16/half-float support #344
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FWIW I think we've got basically no trans/language support for |
The PowerPC 64 architecture also supports a |
This was referenced Mar 16, 2018
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I was implementing the
v{min,max}v
ARM and AArch64 intrinsics and ran into a couple of them that require passing<4 x half>
vectors to llvm and returninghalf
types:pub unsafe fn vmaxv_f16 (a: f16x4_t a) -> f16
pub unsafe fn vmaxvq_f16 (a: f6x8_t a) -> f16
pub unsafe fn vminv_f16 (a: f16x4_t a) -> f16
pub unsafe fn vminvq_f16 (a: f16x8_t a) -> f16
For example,
vmaxv_f16
should map to:call half @llvm.aarch64.neon.fminv.f16.v4f16(<4 x half>)
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