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Update aarch64 linux feature detection #1146

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merged 9 commits into from
May 28, 2021
Merged

Update aarch64 linux feature detection #1146

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b6f50ee
Update aarch64 linux feature detection
adamgemmell Apr 28, 2021
f3f1646
Rename fptoint to frintts
adamgemmell May 19, 2021
e62f4e8
Remove crypto feature. Add AES/SHA2 features to all arm/aarch64 platf…
adamgemmell May 19, 2021
0958d8e
Update core_arch tests for removal of crypto feature in rustc
adamgemmell May 19, 2021
6a3b07b
Fix aarch64 freebsd compilation
adamgemmell May 19, 2021
cf5fb09
Rustfmt style changes
adamgemmell May 20, 2021
e72d133
Replace simd_test macro
adamgemmell May 21, 2021
b639f40
Readd crypto for arm, as it's required for cryptographic intrinsics o…
adamgemmell May 26, 2021
693ae3c
Style changes
adamgemmell May 27, 2021
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141 changes: 113 additions & 28 deletions crates/core_arch/src/arm_shared/crypto.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -51,9 +51,16 @@ extern "C" {
#[cfg(test)]
use stdarch_test::assert_instr;

// Rust compilers without 8a57820bca64a252489790a57cb5ea23db6f9198 need crypto (hence the bootstrap check)
// LLVM builds without b8baa2a9132498ea286dbb0d03f005760ecc6fdb need crypto for arm (hence the target_arch check)

/// AES single round encryption.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(aese))]
pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
Expand All @@ -62,7 +69,11 @@ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {

/// AES single round decryption.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(aesd))]
pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
Expand All @@ -71,7 +82,11 @@ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {

/// AES mix columns.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(aesmc))]
pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
Expand All @@ -80,7 +95,11 @@ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {

/// AES inverse mix columns.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(aesimc))]
pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
Expand All @@ -89,7 +108,11 @@ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {

/// SHA1 fixed rotate.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha1h))]
pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
Expand All @@ -98,7 +121,11 @@ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {

/// SHA1 hash update accelerator, choose.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha1c))]
pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
Expand All @@ -107,7 +134,11 @@ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->

/// SHA1 hash update accelerator, majority.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha1m))]
pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
Expand All @@ -116,7 +147,11 @@ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->

/// SHA1 hash update accelerator, parity.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha1p))]
pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
Expand All @@ -125,7 +160,11 @@ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->

/// SHA1 schedule update accelerator, first part.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha1su0))]
pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
Expand All @@ -134,7 +173,11 @@ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_

/// SHA1 schedule update accelerator, second part.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha1su1))]
pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
Expand All @@ -143,7 +186,11 @@ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t

/// SHA256 hash update accelerator.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha256h))]
pub unsafe fn vsha256hq_u32(
Expand All @@ -156,7 +203,11 @@ pub unsafe fn vsha256hq_u32(

/// SHA256 hash update accelerator, upper part.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha256h2))]
pub unsafe fn vsha256h2q_u32(
Expand All @@ -169,7 +220,11 @@ pub unsafe fn vsha256h2q_u32(

/// SHA256 schedule update accelerator, first part.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha256su0))]
pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
Expand All @@ -178,7 +233,11 @@ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t

/// SHA256 schedule update accelerator, second part.
#[inline]
#[target_feature(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(sha256su1))]
pub unsafe fn vsha256su1q_u32(
Expand All @@ -196,7 +255,11 @@ mod tests {
use std::mem;
use stdarch_test::simd_test;

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
unsafe fn test_vaeseq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
Expand All @@ -209,7 +272,11 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
unsafe fn test_vaesdq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
Expand All @@ -220,7 +287,11 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
unsafe fn test_vaesmcq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let r: u8x16 = mem::transmute(vaesmcq_u8(data));
Expand All @@ -230,7 +301,11 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
unsafe fn test_vaesimcq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let r: u8x16 = mem::transmute(vaesimcq_u8(data));
Expand All @@ -240,13 +315,15 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha1h_u32() {
assert_eq!(vsha1h_u32(0x1234), 0x048d);
assert_eq!(vsha1h_u32(0x5678), 0x159e);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha1su0q_u32() {
let r: u32x4 = mem::transmute(vsha1su0q_u32(
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
Expand All @@ -256,7 +333,8 @@ mod tests {
assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha1su1q_u32() {
let r: u32x4 = mem::transmute(vsha1su1q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -268,7 +346,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha1cq_u32() {
let r: u32x4 = mem::transmute(vsha1cq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -281,7 +360,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha1pq_u32() {
let r: u32x4 = mem::transmute(vsha1pq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -294,7 +374,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha1mq_u32() {
let r: u32x4 = mem::transmute(vsha1mq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -307,7 +388,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha256hq_u32() {
let r: u32x4 = mem::transmute(vsha256hq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -320,7 +402,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha256h2q_u32() {
let r: u32x4 = mem::transmute(vsha256h2q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -333,7 +416,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha256su0q_u32() {
let r: u32x4 = mem::transmute(vsha256su0q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -345,7 +429,8 @@ mod tests {
);
}

#[simd_test(enable = "crypto")]
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
unsafe fn test_vsha256su1q_u32() {
let r: u32x4 = mem::transmute(vsha256su1q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand Down
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