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Clean up aarch64 crypto feature #1192

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merged 2 commits into from
Aug 2, 2021
Merged

Clean up aarch64 crypto feature #1192

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161b095
Replace the crypto feature with aes in generated intrinsics for aarch64
adamgemmell Jun 2, 2021
a2aac52
Remove the bootstrap directive for cryptographic target_features
adamgemmell Jul 29, 2021
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4 changes: 2 additions & 2 deletions crates/core_arch/src/aarch64/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4672,7 +4672,7 @@ pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {

/// Polynomial multiply long
#[inline]
#[target_feature(enable = "neon,crypto")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(test, assert_instr(pmull))]
pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 {
#[allow(improper_ctypes)]
Expand All @@ -4695,7 +4695,7 @@ pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {

/// Polynomial multiply long
#[inline]
#[target_feature(enable = "neon,crypto")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(test, assert_instr(pmull))]
pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
vmull_p64(simd_extract(a, 1), simd_extract(b, 1))
Expand Down
183 changes: 57 additions & 126 deletions crates/core_arch/src/arm_shared/crypto.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -51,147 +51,102 @@ extern "C" {
#[cfg(test)]
use stdarch_test::assert_instr;

// Rust compilers without 8a57820bca64a252489790a57cb5ea23db6f9198 need crypto (hence the bootstrap check)
// LLVM builds without b8baa2a9132498ea286dbb0d03f005760ecc6fdb need crypto for arm (hence the target_arch check)
// TODO: Use AES for ARM when the minimum LLVM version includes b8baa2a9132498ea286dbb0d03f005760ecc6fdb

/// AES single round encryption.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(aese))]
pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
vaeseq_u8_(data, key)
}

/// AES single round decryption.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(aesd))]
pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
vaesdq_u8_(data, key)
}

/// AES mix columns.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(aesmc))]
pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
vaesmcq_u8_(data)
}

/// AES inverse mix columns.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(aesimc))]
pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
vaesimcq_u8_(data)
}

/// SHA1 fixed rotate.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha1h))]
pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
vsha1h_u32_(hash_e)
}

/// SHA1 hash update accelerator, choose.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha1c))]
pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
vsha1cq_u32_(hash_abcd, hash_e, wk)
}

/// SHA1 hash update accelerator, majority.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha1m))]
pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
vsha1mq_u32_(hash_abcd, hash_e, wk)
}

/// SHA1 hash update accelerator, parity.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha1p))]
pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
vsha1pq_u32_(hash_abcd, hash_e, wk)
}

/// SHA1 schedule update accelerator, first part.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha1su0))]
pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
vsha1su0q_u32_(w0_3, w4_7, w8_11)
}

/// SHA1 schedule update accelerator, second part.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha1su1))]
pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
vsha1su1q_u32_(tw0_3, w12_15)
}

/// SHA256 hash update accelerator.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha256h))]
pub unsafe fn vsha256hq_u32(
hash_abcd: uint32x4_t,
Expand All @@ -203,12 +158,8 @@ pub unsafe fn vsha256hq_u32(

/// SHA256 hash update accelerator, upper part.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha256h2))]
pub unsafe fn vsha256h2q_u32(
hash_efgh: uint32x4_t,
Expand All @@ -220,25 +171,17 @@ pub unsafe fn vsha256h2q_u32(

/// SHA256 schedule update accelerator, first part.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha256su0))]
pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
vsha256su0q_u32_(w0_3, w4_7)
}

/// SHA256 schedule update accelerator, second part.
#[inline]
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
#[cfg_attr(
not(any(bootstrap, target_arch = "arm")),
target_feature(enable = "sha2")
)]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
#[cfg_attr(test, assert_instr(sha256su1))]
pub unsafe fn vsha256su1q_u32(
tw0_3: uint32x4_t,
Expand All @@ -255,11 +198,8 @@ mod tests {
use std::mem;
use stdarch_test::simd_test;

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
unsafe fn test_vaeseq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
Expand All @@ -272,11 +212,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
unsafe fn test_vaesdq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
Expand All @@ -287,11 +224,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
unsafe fn test_vaesmcq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let r: u8x16 = mem::transmute(vaesmcq_u8(data));
Expand All @@ -301,11 +235,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(
all(not(bootstrap), target_arch = "aarch64"),
simd_test(enable = "aes")
)]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
unsafe fn test_vaesimcq_u8() {
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
let r: u8x16 = mem::transmute(vaesimcq_u8(data));
Expand All @@ -315,15 +246,15 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha1h_u32() {
assert_eq!(vsha1h_u32(0x1234), 0x048d);
assert_eq!(vsha1h_u32(0x5678), 0x159e);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha1su0q_u32() {
let r: u32x4 = mem::transmute(vsha1su0q_u32(
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
Expand All @@ -333,8 +264,8 @@ mod tests {
assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha1su1q_u32() {
let r: u32x4 = mem::transmute(vsha1su1q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -346,8 +277,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha1cq_u32() {
let r: u32x4 = mem::transmute(vsha1cq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -360,8 +291,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha1pq_u32() {
let r: u32x4 = mem::transmute(vsha1pq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -374,8 +305,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha1mq_u32() {
let r: u32x4 = mem::transmute(vsha1mq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -388,8 +319,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha256hq_u32() {
let r: u32x4 = mem::transmute(vsha256hq_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -402,8 +333,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha256h2q_u32() {
let r: u32x4 = mem::transmute(vsha256h2q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -416,8 +347,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha256su0q_u32() {
let r: u32x4 = mem::transmute(vsha256su0q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand All @@ -429,8 +360,8 @@ mod tests {
);
}

#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
unsafe fn test_vsha256su1q_u32() {
let r: u32x4 = mem::transmute(vsha256su1q_u32(
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
Expand Down
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