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Don't require AVX512 for 128/256-bit GFNI & VPCLMULQDQ intrinsics #1349

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Merged
merged 2 commits into from
Oct 30, 2022
Merged

Don't require AVX512 for 128/256-bit GFNI & VPCLMULQDQ intrinsics #1349

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7132e92
Don't require AVX512 for 128/256-bit GFNI intrinsics
Amanieu Oct 29, 2022
ec5a1bb
Don't require AVX512 for 256-bit VPCLMULQDQ intrinsics
Amanieu Oct 29, 2022
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18 changes: 9 additions & 9 deletions crates/core_arch/src/x86/avx512gfni.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ pub unsafe fn _mm512_maskz_gf2p8mul_epi8(k: __mmask64, a: __m512i, b: __m512i) -
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8mul_epi8)
#[inline]
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
#[target_feature(enable = "avx512gfni,avx")]
#[cfg_attr(test, assert_instr(vgf2p8mulb))]
pub unsafe fn _mm256_gf2p8mul_epi8(a: __m256i, b: __m256i) -> __m256i {
transmute(vgf2p8mulb_256(a.as_i8x32(), b.as_i8x32()))
Expand Down Expand Up @@ -177,8 +177,8 @@ pub unsafe fn _mm256_maskz_gf2p8mul_epi8(k: __mmask32, a: __m256i, b: __m256i) -
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8mul_epi8)
#[inline]
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vgf2p8mulb))]
#[target_feature(enable = "avx512gfni")]
#[cfg_attr(test, assert_instr(gf2p8mulb))]
pub unsafe fn _mm_gf2p8mul_epi8(a: __m128i, b: __m128i) -> __m128i {
transmute(vgf2p8mulb_128(a.as_i8x16(), b.as_i8x16()))
}
Expand Down Expand Up @@ -307,7 +307,7 @@ pub unsafe fn _mm512_mask_gf2p8affine_epi64_epi8<const B: i32>(
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8affine_epi8)
#[inline]
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
#[target_feature(enable = "avx512gfni,avx")]
#[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))]
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm256_gf2p8affine_epi64_epi8<const B: i32>(x: __m256i, a: __m256i) -> __m256i {
Expand Down Expand Up @@ -380,8 +380,8 @@ pub unsafe fn _mm256_mask_gf2p8affine_epi64_epi8<const B: i32>(
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affine_epi8)
#[inline]
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))]
#[target_feature(enable = "avx512gfni")]
#[cfg_attr(test, assert_instr(gf2p8affineqb, B = 0))]
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm_gf2p8affine_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) -> __m128i {
static_assert_imm8!(B);
Expand Down Expand Up @@ -534,7 +534,7 @@ pub unsafe fn _mm512_mask_gf2p8affineinv_epi64_epi8<const B: i32>(
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8affineinv_epi64_epi8)
#[inline]
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
#[target_feature(enable = "avx512gfni,avx")]
#[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))]
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm256_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m256i, a: __m256i) -> __m256i {
Expand Down Expand Up @@ -613,8 +613,8 @@ pub unsafe fn _mm256_mask_gf2p8affineinv_epi64_epi8<const B: i32>(
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affineinv_epi64_epi8)
#[inline]
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))]
#[target_feature(enable = "avx512gfni")]
#[cfg_attr(test, assert_instr(gf2p8affineinvqb, B = 0))]
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) -> __m128i {
static_assert_imm8!(B);
Expand Down
2 changes: 1 addition & 1 deletion crates/core_arch/src/x86/avx512vpclmulqdq.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ pub unsafe fn _mm512_clmulepi64_epi128<const IMM8: i32>(a: __m512i, b: __m512i)
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_clmulepi64_epi128)
#[inline]
#[target_feature(enable = "avx512vpclmulqdq,avx512vl")]
#[target_feature(enable = "avx512vpclmulqdq")]
#[cfg_attr(test, assert_instr(vpclmul, IMM8 = 0))]
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm256_clmulepi64_epi128<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
Expand Down
12 changes: 9 additions & 3 deletions crates/stdarch-verify/tests/x86-intel.rs
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Expand Up @@ -471,9 +471,15 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
continue;
}

// Some AMD CPUs support VAES without AVX512, even though the Intel
// documentation states that those instructions require AVX512VL.
if *cpuid == "AVX512VL" && intel.cpuid.contains(&"VAES".to_string()) {
// Some CPUs support VAES/GFNI/VPCLMULQDQ without AVX512, even though
// the Intel documentation states that those instructions require
// AVX512VL.
if *cpuid == "AVX512VL"
&& intel
.cpuid
.iter()
.any(|x| matches!(&**x, "VAES" | "GFNI" | "VPCLMULQDQ"))
{
continue;
}

Expand Down