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Fix some test naming, and refactor stdarch-verify in general #1707

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Feb 7, 2025
Merged

Fix some test naming, and refactor stdarch-verify in general #1707

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211c94c
Fix names of several tests
sayantn Feb 5, 2025
11dfa41
Remove CSR accessing tests as they are immediate UB
sayantn Feb 5, 2025
5a053a6
Move all x86 std_detect tests to `x86-specific.rs` to reduce duplication
sayantn Feb 5, 2025
9696baf
Small refactorings in `x86-intel.rs`
sayantn Feb 5, 2025
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2 changes: 1 addition & 1 deletion crates/core_arch/src/x86/eflags.rs
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Expand Up @@ -73,7 +73,7 @@ mod tests {
#[test]
#[cfg_attr(miri, ignore)] // Uses inline assembly
#[allow(deprecated)]
fn test_eflags() {
fn test_readeflags() {
unsafe {
// reads eflags, writes them back, reads them again,
// and compare for equality:
Expand Down
49 changes: 37 additions & 12 deletions crates/core_arch/src/x86/f16c.rs
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Expand Up @@ -98,23 +98,48 @@ mod tests {
use crate::{core_arch::x86::*, mem::transmute};
use stdarch_test::simd_test;

const F16_ONE: i16 = 0x3c00;
const F16_TWO: i16 = 0x4000;
const F16_THREE: i16 = 0x4200;
const F16_FOUR: i16 = 0x4400;
const F16_FIVE: i16 = 0x4500;
const F16_SIX: i16 = 0x4600;
const F16_SEVEN: i16 = 0x4700;
const F16_EIGHT: i16 = 0x4800;

#[simd_test(enable = "f16c")]
unsafe fn test_mm_cvtph_ps() {
let array = [1_f32, 2_f32, 3_f32, 4_f32];
let float_vec: __m128 = transmute(array);
let halfs: __m128i = _mm_cvtps_ph::<0>(float_vec);
let floats: __m128 = _mm_cvtph_ps(halfs);
let result: [f32; 4] = transmute(floats);
assert_eq!(result, array);
let a = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
let r = _mm_cvtph_ps(a);
let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
assert_eq_m128(r, e);
}

#[simd_test(enable = "f16c")]
unsafe fn test_mm256_cvtph_ps() {
let array = [1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32];
let float_vec: __m256 = transmute(array);
let halfs: __m128i = _mm256_cvtps_ph::<0>(float_vec);
let floats: __m256 = _mm256_cvtph_ps(halfs);
let result: [f32; 8] = transmute(floats);
assert_eq!(result, array);
let a = _mm_set_epi16(
F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT,
);
let r = _mm256_cvtph_ps(a);
let e = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
assert_eq_m256(r, e);
}

#[simd_test(enable = "f16c")]
unsafe fn test_mm_cvtps_ph() {
let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
let r = _mm_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a);
let e = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
assert_eq_m128i(r, e);
}

#[simd_test(enable = "f16c")]
unsafe fn test_mm256_cvtps_ph() {
let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
let r = _mm256_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a);
let e = _mm_set_epi16(
F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT,
);
assert_eq_m128i(r, e);
}
}
8 changes: 4 additions & 4 deletions crates/core_arch/src/x86/rdtsc.rs
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Expand Up @@ -63,15 +63,15 @@ mod tests {
use stdarch_test::simd_test;

#[simd_test(enable = "sse2")]
unsafe fn _rdtsc() {
let r = rdtsc::_rdtsc();
unsafe fn test_rdtsc() {
let r = _rdtsc();
assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
}

#[simd_test(enable = "sse2")]
unsafe fn _rdtscp() {
unsafe fn test_rdtscp() {
let mut aux = 0;
let r = rdtsc::__rdtscp(&mut aux);
let r = __rdtscp(&mut aux);
assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
}
}
6 changes: 3 additions & 3 deletions crates/core_arch/src/x86/rtm.rs
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Expand Up @@ -120,13 +120,13 @@ mod tests {
use crate::core_arch::x86::*;

#[simd_test(enable = "rtm")]
unsafe fn test_xbegin_xend() {
unsafe fn test_xbegin() {
let mut x = 0;
for _ in 0..10 {
let code = rtm::_xbegin();
let code = _xbegin();
if code == _XBEGIN_STARTED {
x += 1;
rtm::_xend();
_xend();
assert_eq!(x, 1);
break;
}
Expand Down
119 changes: 4 additions & 115 deletions crates/core_arch/src/x86/sse.rs
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Expand Up @@ -1738,7 +1738,7 @@ pub unsafe fn _MM_GET_ROUNDING_MODE() -> u32 {
note = "see `_mm_setcsr` documentation - use inline assembly instead"
)]
pub unsafe fn _MM_SET_EXCEPTION_MASK(x: u32) {
_mm_setcsr((_mm_getcsr() & !_MM_MASK_MASK) | x)
_mm_setcsr((_mm_getcsr() & !_MM_MASK_MASK) | (x & _MM_MASK_MASK))
}

/// See [`_mm_setcsr`](fn._mm_setcsr.html)
Expand All @@ -1754,7 +1754,7 @@ pub unsafe fn _MM_SET_EXCEPTION_MASK(x: u32) {
note = "see `_mm_setcsr` documentation - use inline assembly instead"
)]
pub unsafe fn _MM_SET_EXCEPTION_STATE(x: u32) {
_mm_setcsr((_mm_getcsr() & !_MM_EXCEPT_MASK) | x)
_mm_setcsr((_mm_getcsr() & !_MM_EXCEPT_MASK) | (x & _MM_EXCEPT_MASK))
}

/// See [`_mm_setcsr`](fn._mm_setcsr.html)
Expand All @@ -1770,9 +1770,7 @@ pub unsafe fn _MM_SET_EXCEPTION_STATE(x: u32) {
note = "see `_mm_setcsr` documentation - use inline assembly instead"
)]
pub unsafe fn _MM_SET_FLUSH_ZERO_MODE(x: u32) {
let val = (_mm_getcsr() & !_MM_FLUSH_ZERO_MASK) | x;
// println!("setting csr={:x}", val);
_mm_setcsr(val)
_mm_setcsr((_mm_getcsr() & !_MM_FLUSH_ZERO_MASK) | (x & _MM_FLUSH_ZERO_MASK))
}

/// See [`_mm_setcsr`](fn._mm_setcsr.html)
Expand All @@ -1788,7 +1786,7 @@ pub unsafe fn _MM_SET_FLUSH_ZERO_MODE(x: u32) {
note = "see `_mm_setcsr` documentation - use inline assembly instead"
)]
pub unsafe fn _MM_SET_ROUNDING_MODE(x: u32) {
_mm_setcsr((_mm_getcsr() & !_MM_ROUND_MASK) | x)
_mm_setcsr((_mm_getcsr() & !_MM_ROUND_MASK) | (x & _MM_ROUND_MASK))
}

/// See [`_mm_prefetch`](fn._mm_prefetch.html).
Expand Down Expand Up @@ -2901,57 +2899,6 @@ mod tests {
}
}

#[allow(deprecated)] // FIXME: This test uses deprecated CSR access functions
#[simd_test(enable = "sse")]
#[cfg_attr(miri, ignore)] // Uses _mm_setcsr, which is not supported by Miri
unsafe fn test_mm_comieq_ss_vs_ucomieq_ss() {
// If one of the arguments is a quiet NaN `comieq_ss` should signal an
// Invalid Operation Exception while `ucomieq_ss` should not.
let aa = &[3.0f32, NAN, 23.0, NAN];
let bb = &[3.0f32, 47.5, NAN, NAN];

let ee = &[1i32, 0, 0, 0];
let exc = &[0u32, 1, 1, 1]; // Should comieq_ss signal an exception?

for i in 0..4 {
let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);

_MM_SET_EXCEPTION_STATE(0);
let r1 = _mm_comieq_ss(*black_box(&a), b);
let s1 = _MM_GET_EXCEPTION_STATE();

_MM_SET_EXCEPTION_STATE(0);
let r2 = _mm_ucomieq_ss(*black_box(&a), b);
let s2 = _MM_GET_EXCEPTION_STATE();

assert_eq!(
ee[i], r1,
"_mm_comeq_ss({:?}, {:?}) = {}, expected: {} (i={})",
a, b, r1, ee[i], i
);
assert_eq!(
ee[i], r2,
"_mm_ucomeq_ss({:?}, {:?}) = {}, expected: {} (i={})",
a, b, r2, ee[i], i
);
assert_eq!(
s1,
exc[i] * _MM_EXCEPT_INVALID,
"_mm_comieq_ss() set exception flags: {} (i={})",
s1,
i
);
assert_eq!(
s2,
0, // ucomieq_ss should not signal an exception
"_mm_ucomieq_ss() set exception flags: {} (i={})",
s2,
i
);
}
}

#[simd_test(enable = "sse")]
unsafe fn test_mm_cvtss_si32() {
let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
Expand Down Expand Up @@ -3320,64 +3267,6 @@ mod tests {
_mm_sfence();
}

#[allow(deprecated)] // FIXME: This tests functions that are immediate UB
#[simd_test(enable = "sse")]
#[cfg_attr(miri, ignore)] // Miri does not support accesing the CSR
unsafe fn test_mm_getcsr_setcsr_1() {
let saved_csr = _mm_getcsr();

let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0);
let b = _mm_setr_ps(0.001, 0.0, 0.0, 1.0);

_MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON);
let r = _mm_mul_ps(*black_box(&a), *black_box(&b));

_mm_setcsr(saved_csr);

let exp = _mm_setr_ps(0.0, 0.0, 0.0, 1.0);
assert_eq_m128(r, exp); // first component is a denormalized f32
}

#[allow(deprecated)] // FIXME: This tests functions that are immediate UB
#[simd_test(enable = "sse")]
#[cfg_attr(miri, ignore)] // Miri does not support accesing the CSR
unsafe fn test_mm_getcsr_setcsr_2() {
// Same as _mm_setcsr_1 test, but with opposite flag value.

let saved_csr = _mm_getcsr();

let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0);
let b = _mm_setr_ps(0.001, 0.0, 0.0, 1.0);

_MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_OFF);
let r = _mm_mul_ps(*black_box(&a), *black_box(&b));

_mm_setcsr(saved_csr);

let exp = _mm_setr_ps(1.1e-39, 0.0, 0.0, 1.0);
assert_eq_m128(r, exp); // first component is a denormalized f32
}

#[allow(deprecated)] // FIXME: This tests functions that are immediate UB
#[simd_test(enable = "sse")]
#[cfg_attr(miri, ignore)] // Miri does not support accesing the CSR
unsafe fn test_mm_getcsr_setcsr_underflow() {
_MM_SET_EXCEPTION_STATE(0);

let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0);
let b = _mm_setr_ps(1e-5, 0.0, 0.0, 1.0);

assert_eq!(_MM_GET_EXCEPTION_STATE(), 0); // just to be sure

let r = _mm_mul_ps(*black_box(&a), *black_box(&b));

let exp = _mm_setr_ps(1.1e-41, 0.0, 0.0, 1.0);
assert_eq_m128(r, exp);

let underflow = _MM_GET_EXCEPTION_STATE() & _MM_EXCEPT_UNDERFLOW != 0;
assert!(underflow);
}

#[simd_test(enable = "sse")]
unsafe fn test_MM_TRANSPOSE4_PS() {
let mut a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
Expand Down
10 changes: 2 additions & 8 deletions crates/core_arch/src/x86/sse41.rs
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Expand Up @@ -1310,7 +1310,7 @@ mod tests {
}

#[simd_test(enable = "sse4.1")]
unsafe fn test_mm_min_epi8_1() {
unsafe fn test_mm_min_epi8() {
#[rustfmt::skip]
let a = _mm_setr_epi8(
1, 4, 5, 8, 9, 12, 13, 16,
Expand All @@ -1328,10 +1328,7 @@ mod tests {
17, 19, 21, 23, 25, 27, 29, 31,
);
assert_eq_m128i(r, e);
}

#[simd_test(enable = "sse4.1")]
unsafe fn test_mm_min_epi8_2() {
#[rustfmt::skip]
let a = _mm_setr_epi8(
1, -4, -5, 8, -9, -12, 13, -16,
Expand Down Expand Up @@ -1361,16 +1358,13 @@ mod tests {
}

#[simd_test(enable = "sse4.1")]
unsafe fn test_mm_min_epi32_1() {
unsafe fn test_mm_min_epi32() {
let a = _mm_setr_epi32(1, 4, 5, 8);
let b = _mm_setr_epi32(2, 3, 6, 7);
let r = _mm_min_epi32(a, b);
let e = _mm_setr_epi32(1, 3, 5, 7);
assert_eq_m128i(r, e);
}

#[simd_test(enable = "sse4.1")]
unsafe fn test_mm_min_epi32_2() {
let a = _mm_setr_epi32(-1, 4, 5, -7);
let b = _mm_setr_epi32(-2, 3, -6, 8);
let r = _mm_min_epi32(a, b);
Expand Down
4 changes: 0 additions & 4 deletions crates/core_arch/src/x86/xsave.rs
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Expand Up @@ -185,10 +185,6 @@ mod tests {
}
}

// We cannot test for `_xsave`, `xrstor`, `_xsetbv`, `_xsaveopt`, `_xsaves`, `_xrstors` as they
// are privileged instructions and will need access to kernel mode to execute and test them.
// see https://github.com/rust-lang/stdarch/issues/209

#[cfg_attr(stdarch_intel_sde, ignore)]
#[simd_test(enable = "xsave")]
#[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
Expand Down
2 changes: 1 addition & 1 deletion crates/core_arch/src/x86_64/tbm.rs
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Expand Up @@ -206,7 +206,7 @@ mod tests {
}

#[simd_test(enable = "tbm")]
unsafe fn test_t1mksc_u64() {
unsafe fn test_t1mskc_u64() {
assert_eq!(
_t1mskc_u64(0b0101_0111u64),
0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64
Expand Down
4 changes: 0 additions & 4 deletions crates/core_arch/src/x86_64/xsave.rs
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Expand Up @@ -149,10 +149,6 @@ mod tests {
}
}

// We cannot test `_xsave64`, `_xrstor64`, `_xsaveopt64`, `_xsaves64` and `_xrstors64` directly
// as they are privileged instructions and will need access to the kernel to run and test them.
// See https://github.com/rust-lang/stdarch/issues/209

#[cfg_attr(stdarch_intel_sde, ignore)]
#[simd_test(enable = "xsave")]
#[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
Expand Down
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