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RISC-V: Tidying of features / extensions #1752

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merged 3 commits into from
Mar 25, 2025
Merged

RISC-V: Tidying of features / extensions #1752

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e7c1f12
reorder all RISC-V features for maintenance
a4lg Mar 21, 2025
8f28efe
reword RISC-V feature documentation
a4lg Mar 21, 2025
dcf4f02
tentatively remove the "B" RISC-V extension from the documentation
a4lg Mar 21, 2025
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166 changes: 87 additions & 79 deletions crates/std_detect/src/detect/arch/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ features! {
/// * RV32I: `"rv32i"`
/// * RV64I: `"rv64i"`
/// * A: `"a"`
/// * B: `"b"`
/// * Bit-Manipulation Extensions:
/// * Zba: `"zba"`
/// * Zbb: `"zbb"`
/// * Zbc: `"zbc"`
Expand Down Expand Up @@ -89,124 +89,132 @@ features! {
///
/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
#[stable(feature = "riscv_ratified", since = "1.78.0")]

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
without cfg check: true;
/// RV32I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
without cfg check: true;
/// "Zifencei" Instruction-Fetch Fence
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
without cfg check: true;
/// "Zihintpause" Pause Hint
/// RV32E Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
without cfg check: true;
/// RV64I Base Integer Instruction Set
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
/// "M" Standard Extension for Integer Multiplication and Division
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
/// "A" Standard Extension for Atomic Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
without cfg check: true;
/// RV128I Base Integer Instruction Set

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
without cfg check: true;
/// "Zicsr", Control and Status Register (CSR) Instructions
/// "Zicsr" Extension for Control and Status Register (CSR) Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
without cfg check: true;
/// "Zicntr", Standard Extension for Base Counters and Timers
/// "Zicntr" Extension for Base Counters and Timers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
without cfg check: true;
/// "Zihpm", Standard Extension for Hardware Performance Counters
/// "Zihpm" Extension for Hardware Performance Counters

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
without cfg check: true;
/// "Zifencei" Extension for Instruction-Fetch Fence
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
without cfg check: true;
/// "Zihintpause" Extension for Pause Hint

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
/// "M" Extension for Integer Multiplication and Division

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
/// "A" Extension for Atomic Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
without cfg check: true;
/// "Zam" Extension for Misaligned Atomics
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
without cfg check: true;
/// "Ztso" Extension for Total Store Ordering

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
/// "F" Standard Extension for Single-Precision Floating-Point
/// "F" Extension for Single-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
/// "D" Standard Extension for Double-Precision Floating-Point
/// "D" Extension for Double-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
without cfg check: true;
/// "Q" Standard Extension for Quad-Precision Floating-Point
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
/// "C" Standard Extension for Compressed Instructions
/// "Q" Extension for Quad-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
/// "Zfh" Extension for Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
/// "Zfhmin" Extension for Minimal Half-Precision Floating-Point

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
/// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
/// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
/// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
/// "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
/// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
/// "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
without cfg check: true;
/// "Ztso" Standard Extension for Total Store Ordering

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
without cfg check: true;
/// RV32E Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
without cfg check: true;
/// RV128I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
without cfg check: true;
/// "J" Standard Extension for Dynamically Translated Languages
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
without cfg check: true;
/// "P" Standard Extension for Packed-SIMD Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
/// "V" Standard Extension for Vector Operations
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
without cfg check: true;
/// "Zam" Standard Extension for Misaligned Atomics
/// "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
without cfg check: true;
/// Supervisor-Level ISA
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
without cfg check: true;
/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
without cfg check: true;
/// "Svpbmt" Standard Extension for Page-Based Memory Types
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
without cfg check: true;
/// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
without cfg check: true;
/// Hypervisor Extension
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
/// "C" Extension for Compressed Instructions

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba";
/// "Zba" Standard Extension for Address Generation Instructions
/// "Zba" Extension for Address Generation
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbb: "zbb";
/// "Zbb" Standard Extension for Basic Bit-Manipulation
/// "Zbb" Extension for Basic Bit-Manipulation
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbc: "zbc";
/// "Zbc" Standard Extension for Carry-less Multiplication
/// "Zbc" Extension for Carry-less Multiplication
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbs: "zbs";
/// "Zbs" Standard Extension for Single-Bit instructions
/// "Zbs" Extension for Single-Bit instructions

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkb: "zbkb";
/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
/// "Zbkb" Extension for Bit-manipulation for Cryptography
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkc: "zbkc";
/// "Zbkc" Standard Extension for Carry-less multiply instructions
/// "Zbkc" Extension for Carry-less multiplication for Cryptography
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkx: "zbkx";
/// "Zbkx" Standard Extension for Crossbar permutation instructions
/// "Zbkx" Extension for Crossbar permutations
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknd: "zknd";
/// "Zknd" Standard Extension for NIST Suite: AES Decryption
/// "Zknd" Cryptography Extension for NIST Suite: AES Decryption
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkne: "zkne";
/// "Zkne" Standard Extension for NIST Suite: AES Encryption
/// "Zkne" Cryptography Extension for NIST Suite: AES Encryption
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknh: "zknh";
/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
/// "Zknh" Cryptography Extension for NIST Suite: Hash Function Instructions
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksed: "zksed";
/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
/// "Zksed" Cryptography Extension for ShangMi Suite: SM4 Block Cipher Instructions
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksh: "zksh";
/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
/// "Zksh" Cryptography Extension for ShangMi Suite: SM3 Hash Function Instructions
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkr: "zkr";
/// "Zkr" Standard Extension for Entropy Source Extension
/// "Zkr" Entropy Source Extension
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkn: "zkn";
/// "Zkn" Standard Extension for NIST Algorithm Suite
/// "Zkn" Cryptography Extension for NIST Algorithm Suite
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zks: "zks";
/// "Zks" Standard Extension for ShangMi Algorithm Suite
/// "Zks" Cryptography Extension for ShangMi Algorithm Suite
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zk: "zk";
/// "Zk" Standard Extension for Standard scalar cryptography extension
/// "Zk" Cryptography Extension for Standard scalar cryptography
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt";
/// "Zkt" Standard Extension for Data Independent Execution Latency
/// "Zkt" Cryptography Extension for Data Independent Execution Latency

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
/// "V" Extension for Vector Operations

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
without cfg check: true;
/// "Svnapot" Extension for NAPOT Translation Contiguity
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
without cfg check: true;
/// "Svpbmt" Extension for Page-Based Memory Types
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
without cfg check: true;
/// "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
without cfg check: true;
/// "H" Extension for Hypervisor Support

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
without cfg check: true;
/// Supervisor-Level ISA
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
without cfg check: true;
/// "J" Extension for Dynamically Translated Languages
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
without cfg check: true;
/// "P" Extension for Packed-SIMD Instructions
}