feat?(riscv): turn off jump tables

Removes some flash accesses that occur as the result of an optimization
when mapping a sequence of integers to an action, such as calling
handler `interrupt7` for interrupt code 7.

Previously, this would compile to something similar to:

```asm
40380538:       34202573                csrr    a0,mcause
4038053c:       0506                    slli    a0,a0,0x1
4038053e:       8105                    srli    a0,a0,0x1
        match code {
40380540:       157d                    addi    a0,a0,-1
40380542:       45f9                    li      a1,30
40380544:       2ca5e163                bltu    a1,a0,40380806 <.LBB2_7+0x2ae>
40380548:       050a                    slli    a0,a0,0x2
4038054a:       3c0075b7                lui     a1,0x3c007
4038054e:       1dc58593                addi    a1,a1,476 # 3c0071dc <.LJTI2_0>
40380552:       952e                    add     a0,a0,a1
40380554:       4108                    lw      a0,0(a0)
40380556:       8502                    jr      a0
```

followed by a bunch of entries corresponding to various `interruptN`
calls. `.LJTI2_0` there is stored in flash, and so this requires some
amount of Flash access and/or induces cache pressure.

Unfortunately, LLVM's ELF lowering is fairly determined to emit these
jump tables as part the [`.rodata` section][elf-lowering-jt-sec], which
makes them difficult to specifically relocate to SRAM on their own to
preserve the optimization. So, this instead disables the otpimzation
globally (for all crates and all paths), but only for examples built
directly from the HAL (downstream crates would need to set this setting
themselves, as with force-frame-pointers).

[elf-lowering-jt-sec]: https://llvm.org/doxygen/TargetLoweringObjectFileImpl_8cpp_source.html#l00942

esp32c3-hal/.cargo/config.toml

@@ -4,6 +4,8 @@ rustflags = [
   "-C", "link-arg=-Tlinkall.x",
   "-C", "force-frame-pointers",
 
+  "-C", "llvm-args=--max-jump-table-size=0",
+
   # comment the cfgs below if you do _not_ wish to emulate atomics.
   # enable the atomic codegen option for RISCV
   "-C", "target-feature=+a",