HardNet - FPGA Implementation of a Neural Network

Overview

This repository contains the implementation of a neural network on an FPGA platform, aimed at deploying the MNIST neural network for digit recognition tasks. Custom neurons have been developed from scratch using the Verilog hardware description language. The project focuses on leveraging FPGA's parallel processing capabilities to accelerate the inference process of the neural network.

Features

• Implementation of a neural network architecture tailored for the MNIST dataset.
• Utilization of Verilog HDL for designing custom neurons, enabling hardware-level acceleration.
• Support for digit recognition tasks using the trained MNIST neural network.
• Modular design facilitating customization and extension for different FPGA platforms and neural network architectures.

Neuron Architecture

Contributions

Contributions to this project are welcome. If you find any issues or have suggestions for improvements, please feel free to open an issue or create a pull request with your proposed changes.

License

This project is licensed under the MIT License.