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1. Master_Thesis Master_Thesis Public

   Correct-by-Construction Hardware Design of A 5-Stage-Pipelined-RV32I CPU

   VHDL 1

2. SystemVerilog SystemVerilog Public

   Main repository for SystemVerilog files

   SystemVerilog

3. EncDecSys EncDecSys Public

   An Encryption/Decryption System Design (Secure Hardware Design Project)

   Verilog

4. GF_Multiplier GF_Multiplier Public

   Design and synthesis a circuit to multiply two elements of Galois Field (2^3) (Secure Hardware Design Assignment)

   VHDL

5. Intelligent_Agent Intelligent_Agent Public

   Intelligent Agent Implementation for Automated Negotiation Agent Competition

   Java 2 1

6. PUF PUF Public

   Design and evaluation of an arbiter-delay-based Physically Unclonable Function (Secure Hardware Design Assignment)

   MATLAB 3 4