GitHub - sameersondur/VHDL-Project-16-bit-RISC-Processor: Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL and tested it by simulating in ModelSim.

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Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL and tested it by simulating in ModelSim.

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Name		Name	Last commit message	Last commit date
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VHDL code		VHDL code
Waveforms		Waveforms
FinalProjectReport_Sondur.pdf		FinalProjectReport_Sondur.pdf
Top Level Block Diagram.jpg		Top Level Block Diagram.jpg

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Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL and tested it by simulating in ModelSim.

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