drm/amd/display: add -msse2 to prevent Clang from emitting libcalls t…

…o undefined SW FP routines

arch/x86/Makefile disables SSE and SSE2 for the whole kernel.  The
AMDGPU drivers modified in this patch re-enable SSE but not SSE2.  Turn
on SSE2 to support emitting double precision floating point instructions
rather than calls to non-existent (usually available from gcc_s or
compiler_rt) floating point helper routines.

Link: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html
Link: ClangBuiltLinux#327
Cc: stable@vger.kernel.org # 4.19
Reported-by: S, Shirish <Shirish.S@amd.com>
Reported-by: Matthias Kaehlcke <mka@google.com>
Suggested-by: James Y Knight <jyknight@google.com>
Suggested-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by:  Matthias Kaehlcke <mka@chromium.org>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[added CONFIG_CC_IS_CLANG]
Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>

drivers/gpu/drm/amd/display/dc/calcs/Makefile

@@ -32,6 +32,12 @@ endif
 
 calcs_ccflags := -mhard-float -msse $(cc_stack_align)
 
+# Use -msse2 only with clang:
+#   https://bugs.freedesktop.org/show_bug.cgi?id=109487
+ifdef CONFIG_CC_IS_CLANG
+calcs_ccflags += -msse2
+endif
+
 CFLAGS_dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
 CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare

drivers/gpu/drm/amd/display/dc/dml/Makefile

@@ -32,6 +32,12 @@ endif
 
 dml_ccflags := -mhard-float -msse $(cc_stack_align)
 
+# Use -msse2 only with clang:
+#   https://bugs.freedesktop.org/show_bug.cgi?id=109487
+ifdef CONFIG_CC_IS_CLANG
+dml_ccflags += -msse2
+endif
+
 CFLAGS_display_mode_lib.o := $(dml_ccflags)
 
 ifdef CONFIG_DRM_AMD_DC_DCN2_0