fud2 support for FIRRTL

[ayakayorihiro]

Edit: I also added support for running the generated System-Verilog via Verilator!

This is a first pass at supporting the Calyx-FIRRTL backend in fud2! As a point of note, we can remove the $extra_primitives argument and the primitives-for-firrtl.sv file once I support primitives in FIRRTL.

Please let me know if there's anything I can improve/should fix here! I also included Setup and Usage notes below, but I can put them elsewhere as needed.

Setup

To generate and run System-Verilog from Calyx-translated FIRRTL, we need the FIRRTL compiler. <ROOT> is the full path to the parent directory of where your repos live (most likely the parent directory of fake and calyx?).
Verilator, yosys, and sbt are also needed.

cd <ROOT>
git clone git@github.com:chipsalliance/firrtl.git
(
                cd firrtl
                sbt compile
                sbt test
                sbt assembly
) 

Then, edit the configuration file (~/.config/fud2.toml) to include the below:

[firrtl]
exe = "<ROOT>/firrtl/utils/bin/firrtl"

Usage

In the below pseudo-commands, <IN_FILE> is the input Calyx file, and <DATA_FILE> is the JSON file containing data.

To generate FIRRTL from Calyx:

fud2 <IN_FILE> --to firrtl

To generate System-Verilog from Calyx-translated FIRRTL:

fud2 <IN_FILE> --to verilog --through firrtl

To run System-Verilog from Calyx-translated FIRRTL using Icarus-Verilog:

fud2 <IN_FILE> --to dat --through icarus-firrtl -s sim.data=<DATA_FILE>

To run System-Verilog from Calyx-translated FIRRTL using Verilator:

fud2 <IN_FILE> --to dat --through verilator-firrtl -s sim.data=<DATA_FILE>

[sampsyo]

AMAZING!!! I'm so glad this was comparatively straightforward to do; everything looks ship shape. I don't really have any comments on the current implementation (except for one super minor one) and think this is good to go!

At some point, when we have a different approach to the primitives, it seems like it could be possible to avoid having separate icarus-firrtl and verilator-firrtl ops, and just rely on the plain ol' icarus and verilator ops. (That is, if I can figure out how to decouple Calyx compilation and Icarus simulation.)

As for the documentation: this is already great!! I have really not written any fud2 docs yet, so I suppose whenever we do that, we should put this stuff there. I'll try to remember to move forward the project of merging fud2 into the Calyx repo, I suppose, so we have a good place to do this!

[sampsyo]

FWIW, you can probably leave off these "empty" assignments; in Ninja, variables that are unassigned are just empty by default.

[ayakayorihiro]

Ah I see! Thanks for letting me know :) (This will all be gone soon so I'll keep things as is for now but will keep this in mind for the future!)

[sampsyo]

FWIW, I was finally able to install FIRRTL and gave this a try all the way through! It works great!!

In recent commits, I also succeeded in simplifying the rules a bit, so now the simulation stages get to start from FIRRTL instead of from Calyx code. That makes them a little smaller and more reusable. The state diagram now looks like this:

Hypothetically, "all we'd need to do" to eliminate the verilator-firrtl and icarus-firrtl stages would be to merge the extra primitives and the compiled Calyx code into one Verilog file. That way, we could feed this merged Verilog directly into the existing verilator and icarus stages. Not sure if that's as simple as just cating them, but maybe!

[ayakayorihiro]

Awesome!! Thank you for trying everything out and fixing things up :)
I think when I get the primitives implemented in Chisel we should be able to get rid of the verilator-firrtl and icarus-firrtl stages simply by getting the FIRRTL versions of the primitives and compiling everything into one Verilog file...? But even with the current setup of things I think a cat would work too!