config: Add higher performance overclock options

ARM3 is now emulated up to 40 MHz, MEMC up to 24 MHz.
sarah-walker-pcem · Oct 12, 2022 · 10bb3bb · 10bb3bb
1 parent 100456d
commit 10bb3bb
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Showing 2 changed files with 38 additions and 12 deletions.
diff --git a/src/main.c b/src/main.c
@@ -278,7 +278,9 @@ static struct
         {"MEMC1",             8, 1},
         {"MEMC1A at 8 MHz",   8, 0},
         {"MEMC1A at 12 MHz", 12, 0},
-        {"MEMC1A at 16 MHz", 16, 0}
+        {"MEMC1A at 16 MHz", 16, 0},
+        {"MEMC1A at 20 MHz", 20, 0},
+        {"MEMC1A at 24 MHz", 24, 0}
 };
 
 static struct
@@ -298,6 +300,8 @@ static struct
         {"ARM3 (33 MHz)", 33, 1, 1},
         {"ARM3 (35 MHz)", 35, 1, 1},
         {"ARM3 (24 MHz)", 24, 1, 1},
+        {"ARM3 (36 MHz)", 36, 1, 1},
+        {"ARM3 (40 MHz)", 40, 1, 1},
 };
 
 void arc_set_cpu(int cpu, int memc)

diff --git a/src/wx-config.cc b/src/wx-config.cc
@@ -36,6 +36,8 @@ enum
         CPU_ARM3_33,
         CPU_ARM3_35,
         CPU_ARM3_24,
+        CPU_ARM3_36,
+        CPU_ARM3_40,
         CPU_MAX
 };
 
@@ -49,7 +51,9 @@ const char *cpu_names[] =
         "ARM3 @ 30 MHz",
         "ARM3 @ 33 MHz",
         "ARM3 @ 35 MHz",
-        "ARM3 @ 24 MHz"
+        "ARM3 @ 24 MHz",
+        "ARM3 @ 36 MHz",
+        "ARM3 @ 40 MHz"
 };
 
 enum
@@ -62,22 +66,24 @@ enum
         CPU_MASK_ARM3_30 = (1 << CPU_ARM3_30),
         CPU_MASK_ARM3_33 = (1 << CPU_ARM3_33),
         CPU_MASK_ARM3_35 = (1 << CPU_ARM3_35),
-        CPU_MASK_ARM3_24 = (1 << CPU_ARM3_24)
+        CPU_MASK_ARM3_24 = (1 << CPU_ARM3_24),
+        CPU_MASK_ARM3_36 = (1 << CPU_ARM3_36),
+        CPU_MASK_ARM3_40 = (1 << CPU_ARM3_40)
 };
 
 #define CPU_ARM2_AND_LATER (CPU_MASK_ARM2 | CPU_MASK_ARM3_20 | CPU_MASK_ARM3_25 | \
                 CPU_MASK_ARM3_26 | CPU_MASK_ARM3_30 | CPU_MASK_ARM3_33 | \
-                CPU_MASK_ARM3_35)
+                CPU_MASK_ARM3_35 | CPU_MASK_ARM3_36 | CPU_MASK_ARM3_40)
 
 #define CPU_ARM250_ONLY (CPU_MASK_ARM250)
 
 #define CPU_ARM3_25_AND_LATER (CPU_MASK_ARM3_25 | CPU_MASK_ARM3_26 | \
-                CPU_MASK_ARM3_30 | CPU_MASK_ARM3_33 | CPU_MASK_ARM3_35)
+                CPU_MASK_ARM3_30 | CPU_MASK_ARM3_33 | CPU_MASK_ARM3_35 | CPU_MASK_ARM3_36 | CPU_MASK_ARM3_40)
 
 #define CPU_ARM3_26_AND_LATER (CPU_MASK_ARM3_26 | CPU_MASK_ARM3_30 | \
-                CPU_MASK_ARM3_33 | CPU_MASK_ARM3_35)
+                CPU_MASK_ARM3_33 | CPU_MASK_ARM3_35 | CPU_MASK_ARM3_36 | CPU_MASK_ARM3_40)
 
-#define CPU_ARM3_33_AND_LATER (CPU_MASK_ARM3_33 | CPU_MASK_ARM3_35)
+#define CPU_ARM3_33_AND_LATER (CPU_MASK_ARM3_33 | CPU_MASK_ARM3_35 | CPU_MASK_ARM3_36 | CPU_MASK_ARM3_40)
 
 #define CPU_ARM3_24_ONLY (CPU_MASK_ARM3_24)
 
@@ -94,6 +100,8 @@ enum
         MEMC_MEMC1A_8,
         MEMC_MEMC1A_12,
         MEMC_MEMC1A_16,
+        MEMC_MEMC1A_20,
+        MEMC_MEMC1A_24,
         MEMC_MAX
 };
 
@@ -102,22 +110,28 @@ const char *memc_names[] =
         "MEMC1",
         "MEMC1a (8 MHz)",
         "MEMC1a (12 MHz)",
-        "MEMC1a (16 MHz - overclocked)"
+        "MEMC1a (16 MHz - overclocked)",
+        "MEMC1a (20 MHz - overclocked)",
+        "MEMC1a (24 MHz - overclocked)"
 };
 
 enum
 {
         MEMC_MASK_MEMC1     = (1 << MEMC_MEMC1),
         MEMC_MASK_MEMC1A_8  = (1 << MEMC_MEMC1A_8),
         MEMC_MASK_MEMC1A_12 = (1 << MEMC_MEMC1A_12),
-        MEMC_MASK_MEMC1A_16 = (1 << MEMC_MEMC1A_16)
+        MEMC_MASK_MEMC1A_16 = (1 << MEMC_MEMC1A_16),
+        MEMC_MASK_MEMC1A_20 = (1 << MEMC_MEMC1A_20),
+        MEMC_MASK_MEMC1A_24 = (1 << MEMC_MEMC1A_24)
 };
 
 #define MEMC_MIN_MEMC1     (MEMC_MASK_MEMC1 | MEMC_MASK_MEMC1A_8 | \
-                MEMC_MASK_MEMC1A_12 | MEMC_MASK_MEMC1A_16)
+                MEMC_MASK_MEMC1A_12 | MEMC_MASK_MEMC1A_16 | MEMC_MASK_MEMC1A_20 | \
+                MEMC_MASK_MEMC1A_24)
 #define MEMC_MIN_MEMC1A    (MEMC_MASK_MEMC1A_8 | MEMC_MASK_MEMC1A_12 | \
-                MEMC_MASK_MEMC1A_16)
-#define MEMC_MIN_MEMC1A_12 (MEMC_MASK_MEMC1A_12 | MEMC_MASK_MEMC1A_16)
+                MEMC_MASK_MEMC1A_16 | MEMC_MASK_MEMC1A_20 | MEMC_MASK_MEMC1A_24)
+#define MEMC_MIN_MEMC1A_12 (MEMC_MASK_MEMC1A_12 | MEMC_MASK_MEMC1A_16 | \
+                MEMC_MASK_MEMC1A_20 | MEMC_MASK_MEMC1A_24)
 
 enum
 {
@@ -847,6 +861,14 @@ void ConfigDialog::OnOK(wxCommandEvent &event)
                 arm_has_swp = arm_has_cp15 = 1;
                 arm_cpu_speed = 35;
                 break;
+                case CPU_ARM3_36:
+                arm_has_swp = arm_has_cp15 = 1;
+                arm_cpu_speed = 36;
+                break;
+                case CPU_ARM3_40:
+                arm_has_swp = arm_has_cp15 = 1;
+                arm_cpu_speed = 40;
+                break;
         }
         arm_cpu_type = config_cpu;