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Since a long time I have the goal to fill and read the Template RAM in Broadcom/Cypress Wi-Fi chips using DMA transfers and then turn the Wi-Fi chip into a full fletched SDR. As SDIO is too slow for continuous signal streams, a PCIE device would be needed. According to the throughput 20 MHz bandwidth should be achievable.
So, if anybody has time or wants to write a thesis at TU Darmstadt (we can also host foreign students), feel free to contact me.
… On 16. Jun 2021, at 15:50, Taranus ***@***.***> wrote:
Hello,
I would like to suggest a project that might interest a lot of people, a high speed and low latency wireless transceiver, using the 2.4 and 5.8 GHz ISM bands.
Indeed, while a couple of 2.4 GHz transceivers are available on the market, allowing proprietary protocols to be implemented, they are limited to low bit-rate (1-2 MBps).
When you need a high-speed wireless link, there is no option other than WLAN chips, with all the known drawbacks (large overhead, jitter, non "real-time", to name a few).
However, these drawbacks are only related to the Wi-Fi protocols implemented in the embedded firmware, the hardware part have almost no limitation, as shown by the Nexmon project.
So, the idea is to develop/patch a firmware that allows to transmit/receive any type of payload, on any channel, with any supported modulation.
A packet filter and re-transmit/ACK engine can also be studied.
The targets that I have in mind are the CYW43455 and CYW43012 chips as they are available as small modules (and I have both).
The system should be connected to an MCU or an FPGA with an SDIO bus; we often don't need the complexity/overhead of a Linux kernel, especially when no IP or Wi-Fi stacks are necessary.
Examples of systems that can be built are low latency and multi-channel audio stream, and live video transmission (e.g. for FPV drone).
Unfortunately, I have no knowledge on the subject (WLAN firmware patching) to achieve this project all alone, and I don't even know if it can be done without any source code from the manufacturer.
What do you think?
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Hello Matthias, an SDR is very low level, too much for my need I guess; as you said it requires a lot of bandwidth and more than an MCU or Media SoC. But, before going further, could you confirm that the D11 core is able to handle non-802.11 frames? Thank you. |
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D11 only controls the low level hardware and that one is designed for wifi frames. For other frames, you would need SDR functionalities.
… On 17. Jun 2021, at 22:26, Taranus ***@***.***> wrote:
Hello Matthias,
an SDR is very low level, too much for my need I guess; as you said it requires a lot of bandwidth and more than an MCU or Media SoC.
I have just started to read the whole literature and videos available on the internet regarding BCM firmware hacking and hope to dump my first ROM image in a couple of days (CYW43012 on PSOC 6 platform).
But, before going further, could you confirm that the D11 core is able to handle non-802.11 frames?
Thank you.
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By non-802.11 frames, I meant frames with a custom header, not the 802.11 MAC one (with the various 6-bytes addresses). Looking at your jammer demo code, I tend to think that the header can be of any kind. To be confirmed by checking the D11 µcode. |
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yes that is possible
… On 18. Jun 2021, at 09:42, Taranus ***@***.***> wrote:
By non-802.11 frames, I meant frames with a custom header, not the 802.11 MAC one (with the various 6-bytes addresses).
Looking at your jammer demo code, I tend to think that the header can be of any kind. To be confirmed by checking the D11 µcode.
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That is correct, you can also have different headers if you want. Only the PLCP needs to fit and it needs to be an OFDM or DSSS frame. But modifying the D11 firmware is tedious.
… On 18. Jun 2021, at 09:42, Taranus ***@***.***> wrote:
By non-802.11 frames, I meant frames with a custom header, not the 802.11 MAC one (with the various 6-bytes addresses).
Looking at your jammer demo code, I tend to think that the header can be of any kind. To be confirmed by checking the D11 µcode.
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Hello,
I would like to suggest a project that might interest a lot of people, a high speed and low latency wireless transceiver, using the 2.4 and 5.8 GHz ISM bands.
Indeed, while a couple of 2.4 GHz transceivers are available on the market, allowing proprietary protocols to be implemented, they are limited to low bit-rate (1-2 MBps).
When you need a high-speed wireless link, there is no option other than WLAN chips, with all the known drawbacks (large overhead, jitter, non "real-time", to name a few).
However, these drawbacks are only related to the Wi-Fi protocols implemented in the embedded firmware, the hardware part have almost no limitation, as shown by the Nexmon project.
So, the idea is to develop/patch a firmware that allows to transmit/receive any type of payload, on any channel, with any supported modulation.
A packet filter and re-transmit/ACK engine can also be studied.
The targets that I have in mind are the CYW43455 and CYW43012 chips as they are available as small modules (and I have both).
The system should be connected to an MCU or an FPGA with an SDIO bus; we often don't need the complexity/overhead of a Linux kernel, especially when no IP or Wi-Fi stacks are necessary.
Examples of systems that can be built are low latency and multi-channel audio stream, and live video transmission (e.g. for FPV drone).
Unfortunately, I have no knowledge on the subject (WLAN firmware patching) to achieve this project all alone, and I don't even know if it can be done without any source code from the manufacturer.
What do you think?
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