bump for bump for chipsalliance/rocket-chip#2841

sequencer · Jan 7, 2022 · e3352bc · e3352bc
1 parent e252e79
commit e3352bc
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Showing 3 changed files with 4 additions and 2 deletions.
diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
@@ -80,13 +80,15 @@ case class BoomCoreParams(
   mulDiv: Option[freechips.rocketchip.rocket.MulDivParams] = Some(MulDivParams(divEarlyOut=true)),
   nBreakpoints: Int = 0, // TODO Fix with better frontend breakpoint unit
   nL2TLBEntries: Int = 512,
+  val nPTECacheEntries: Int = 8, // TODO: check
   nL2TLBWays: Int = 1,
   nLocalInterrupts: Int = 0,
   useNMI: Boolean = false,
   useAtomics: Boolean = true,
   useDebug: Boolean = true,
   useUser: Boolean = true,
   useSupervisor: Boolean = false,
+  useHypervisor: Boolean = false,
   useVM: Boolean = true,
   useSCIE: Boolean = false,
   useRVE: Boolean = false,

diff --git a/src/main/scala/exu/decode.scala b/src/main/scala/exu/decode.scala
@@ -485,7 +485,7 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule
   val cs = Wire(new CtrlSigs()).decode(inst, decode_table)
 
   // Exception Handling
-  io.csr_decode.csr := inst(31,20)
+  io.csr_decode.csr_addr := inst
   val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)
   val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U
   val system_insn = cs.csr_cmd === CSR.I

diff --git a/src/main/scala/lsu/tlb.scala b/src/main/scala/lsu/tlb.scala
@@ -181,7 +181,7 @@ class NBDTLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge
     newEntry.c := cacheable(0)
     newEntry.u := pte.u
     newEntry.g := pte.g
-    newEntry.ae := io.ptw.resp.bits.ae
+    newEntry.ae := io.ptw.resp.bits.ae_final
     newEntry.sr := pte.sr()
     newEntry.sw := pte.sw()
     newEntry.sx := pte.sx()