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Regen BSPs
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Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
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@nategraff-sifive
nategraff-sifive committed Mar 25, 2020
1 parent 267cccd commit 0eabc94
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Showing 9 changed files with 35 additions and 38 deletions.
13 changes: 5 additions & 8 deletions bsp/freedom-e310-arty/openocd.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -43,22 +43,19 @@ switch ${debug_config} {
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu

target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
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13 changes: 5 additions & 8 deletions bsp/freedom-e310-arty/openocd.cjtag.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -43,22 +43,19 @@ switch ${debug_config} {
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu

target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
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22 changes: 14 additions & 8 deletions bsp/sifive-hifive-unleashed/openocd.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,28 @@ ftdi_layout_signal LED -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu0
set _TARGETNAME_1 $_CHIPNAME.cpu1
set _TARGETNAME_2 $_CHIPNAME.cpu2
set _TARGETNAME_3 $_CHIPNAME.cpu3
set _TARGETNAME_4 $_CHIPNAME.cpu4

target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4
target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10040000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
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4 changes: 2 additions & 2 deletions bsp/sifive-hifive-unleashed/settings.mk
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
# Copyright (C) 2020 SiFive Inc
# SPDX-License-Identifier: Apache-2.0

RISCV_ARCH = rv64imafdc
RISCV_ABI = lp64d
RISCV_ARCH = rv64imac
RISCV_ABI = lp64
RISCV_CMODEL = medany
RISCV_SERIES = sifive-5-series

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2 changes: 1 addition & 1 deletion bsp/sifive-hifive1-revb/design.dts
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
/include/ "core.dts"
/ {
chosen {
metal,entry = <&spi0 1 262144>;
metal,entry = <&spi0 1 65536>;
metal,boothart = <&L6>;
stdout-path = "/soc/serial@10013000:115200";
metal,itim = <&itim 0 0>;
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2 changes: 1 addition & 1 deletion bsp/sifive-hifive1-revb/metal.default.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ MEMORY
{
itim (airwx) : ORIGIN = 0x8000000, LENGTH = 0x2000
ram (arw!xi) : ORIGIN = 0x80000000, LENGTH = 0x4000
rom (irx!wa) : ORIGIN = 0x20040000, LENGTH = 0x3a120
rom (irx!wa) : ORIGIN = 0x20010000, LENGTH = 0x6a120
}

SECTIONS
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2 changes: 1 addition & 1 deletion bsp/sifive-hifive1-revb/metal.ramrodata.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ MEMORY
{
itim (airwx) : ORIGIN = 0x8000000, LENGTH = 0x2000
ram (arw!xi) : ORIGIN = 0x80000000, LENGTH = 0x4000
rom (irx!wa) : ORIGIN = 0x20040000, LENGTH = 0x3a120
rom (irx!wa) : ORIGIN = 0x20010000, LENGTH = 0x6a120
}

SECTIONS
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2 changes: 1 addition & 1 deletion bsp/sifive-hifive1-revb/metal.scratchpad.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ MEMORY
{
itim (airwx) : ORIGIN = 0x8000000, LENGTH = 0x2000
ram (arw!xi) : ORIGIN = 0x80000000, LENGTH = 0x4000
rom (irx!wa) : ORIGIN = 0x20040000, LENGTH = 0x3a120
rom (irx!wa) : ORIGIN = 0x20010000, LENGTH = 0x6a120
}

SECTIONS
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13 changes: 5 additions & 8 deletions bsp/sifive-hifive1/openocd.cfg
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,19 @@ ftdi_layout_signal LED -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu

target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
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