Merge pull request #539 from sifive/gcc-10-compatible

Enable gcc 10 compatible
sifive · Sep 9, 2020 · fa3d7d0 · fa3d7d0
2 parents d0b6132 + 1e2a85b
commit fa3d7d0
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Showing 5 changed files with 19 additions and 8 deletions.
diff --git a/bsp/qemu-sifive-u54/core.dts b/bsp/qemu-sifive-u54/core.dts
@@ -16,7 +16,7 @@
 			reg = <0x0>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa = "rv64imafdcsu";
+			riscv,isa = "rv64imafdc";
 			mmu-type = "riscv,sv48";
 			clock-frequency = <0x3b9aca00>;
 			riscv,pmpregions = <8>;

diff --git a/bsp/qemu-sifive-u54/settings.mk b/bsp/qemu-sifive-u54/settings.mk
@@ -1,7 +1,7 @@
 # Copyright (C) 2020 SiFive Inc
 # SPDX-License-Identifier: Apache-2.0
 
-RISCV_ARCH = rv64imafdcsu
+RISCV_ARCH = rv64imafdc
 RISCV_ABI = lp64d
 RISCV_CMODEL = medany
 RISCV_SERIES = None

diff --git a/bsp/qemu-sifive-u54mc/core.dts b/bsp/qemu-sifive-u54mc/core.dts
@@ -16,7 +16,7 @@
 			reg = <0x0>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa = "rv64imafdcsu";
+			riscv,isa = "rv64imafdc";
 			mmu-type = "riscv,sv48";
 			clock-frequency = <0x3b9aca00>;
 			riscv,pmpregions = <8>;

diff --git a/bsp/qemu-sifive-u54mc/settings.mk b/bsp/qemu-sifive-u54mc/settings.mk
@@ -1,7 +1,7 @@
 # Copyright (C) 2020 SiFive Inc
 # SPDX-License-Identifier: Apache-2.0
 
-RISCV_ARCH = rv64imafdcsu
+RISCV_ARCH = rv64imafdc
 RISCV_ABI = lp64d
 RISCV_CMODEL = medany
 RISCV_SERIES = None

diff --git a/scripts/standalone.mk b/scripts/standalone.mk
@@ -168,6 +168,9 @@ RISCV_CXXFLAGS  += --specs=$(SPEC).specs
 RISCV_CFLAGS    += -DMTIME_RATE_HZ_DEF=$(MTIME_RATE_HZ_DEF)
 RISCV_CXXFLAGS  += -DMTIME_RATE_HZ_DEF=$(MTIME_RATE_HZ_DEF)
 
+# gcc10 default use -fno-common, but libmetal has lots of multiple definitions
+RISCV_CFLAGS += -fcommon
+
 # Turn on garbage collection for unused sections
 RISCV_LDFLAGS += -Wl,--gc-sections
 # Turn on linker map file generation
@@ -189,6 +192,10 @@ include $(CONFIGURATION).mk
 
 # Benchmark CFLAGS go after loading the CONFIGURATION so that they can override the optimization level
 
+
+# Checking if we use gcc-10 or not, which need different compiler options for better benchmark scores
+GCC_VER_GTE10 := $(shell echo `${RISCV_GCC} -dumpversion | cut -f1-2 -d.` \>= 10 | bc )
+
 ifeq ($(PROGRAM),dhrystone)
 ifeq ($(DHRY_OPTION),)
 # Ground rules (default)
@@ -205,16 +212,20 @@ endif
 
 ifeq ($(PROGRAM),coremark)
 ifeq ($(RISCV_SERIES),sifive-7-series)
-RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -funroll-all-loops --param max-inline-insns-auto=20 -falign-functions=8 -falign-jumps=8 -falign-loops=8 --param inline-min-speedup=10 -mtune=sifive-7-series -ffast-math
+RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -funroll-all-loops -falign-functions=8 -falign-jumps=8 -falign-loops=8 -finline-limit=1000 -mtune=sifive-7-series -ffast-math
 else
 ifeq ($(RISCV_XLEN),32)
 RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -falign-functions=16 -falign-jumps=4 -falign-loops=4 -finline-limit=1000 -fno-if-conversion2 -fselective-scheduling -fno-tree-dominator-opts -fno-reg-struct-return -fno-rename-registers --param case-values-threshold=8 -fno-crossjumping -freorder-blocks-and-partition -fno-tree-loop-if-convert -fno-tree-sink -fgcse-sm -fno-strict-overflow
 else
 RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -falign-functions=16 -falign-jumps=4 -falign-loops=4 -finline-limit=1000 -fno-if-conversion2 -fselective-scheduling -fno-tree-dominator-opts
-endif
-endif
+endif # RISCV_XLEN==32
+endif # RISCV_SERIES==sifive-7-series
 RISCV_XCFLAGS += -DITERATIONS=$(TARGET_CORE_ITERS)
-endif
+ifeq ($(GCC_VER_GTE10),1)
+# additional options for gcc-10 to get better performance
+RISCV_XCFLAGS += -fno-tree-loop-distribute-patterns --param fsm-scale-path-stmts=3
+endif # GCC_VER_GTE10==1
+endif # PROGRAM==coremark
 
 ifeq ($(findstring freertos,$(PROGRAM)),freertos)
 RISCV_XCFLAGS += -DWAIT_MS=$(TARGET_FREERTOS_WAIT_MS)