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Add QSPI mode and update spi driver.
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QSPI_ALL
      _                                                        _
CS     |______________________________________________________|
         _   _   _   _   _   _   _   _   _   _   _   _   _   _
SCL    _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

Phase ---cmd--|-addr--|-dummy-|-data----------------------------
DQ0     0   4 | 0   4 | 0   4 | 0   4   8  12...
              |       |       |
DQ1     1   5 | 1   5 | 1   5 | 1   5   9  13...
              |       |       |
DQ2     2   6 | 2   6 | 2   6 | 2   6  10  14...
              |       |       |
DQ3     3   7 | 3   7 | 3   7 | 3   7  11  15...

QSPI_ADDR_DATA
      _                                                        _
CS     |______________________________________________________|
         _   _   _   _   _   _   _   _   _   _   _   _   _   _
SCL    _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

Phase  ------cmd------|-addr--|-dummy-|-data--------------------
DQ0     0   1   2   3 | 0   4 | 0   4 | 0   4   8  12...
                      |       |       |
DQ1                   | 1   5 | 1   5 | 1   5   9  13...
                      |       |       |
DQ2                   | 2   6 | 2   6 | 2   6  10  14...
                      |       |       |
DQ3                   | 3   7 | 3   7 | 3   7  11  15...

QSPI_DATA_ONLY
      _                                                        _
CS     |______________________________________________________|
         _   _   _   _   _   _   _   _   _   _   _   _   _   _
SCL    _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

Phase  ------cmd------|------addr-----|-----dummy-----|-data----
DQ0     0   1   2   3 | 0   1   2   3 | 0   1   2   3 | 0   4
                      |               |               |
DQ1                   |               |               | 1   5
                      |               |               |
DQ2                   |               |               | 2   6
                      |               |               |
DQ3                   |               |               | 3   7
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@reclusejack
reclusejack committed Aug 27, 2019
1 parent a4538ef commit 2783ece
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Showing 2 changed files with 130 additions and 3 deletions.
8 changes: 8 additions & 0 deletions metal/spi.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,14 @@ struct metal_spi_config {
unsigned int cs_active_high : 1;
/*! @brief The chip select ID to activate for the SPI transfer */
unsigned int csid;
/*! @brief The spi command frame number (cycles = num * frame_len) */
unsigned int cmd_num;
/*! @brief The spi address frame number */
unsigned int addr_num;
/*! @brief The spi dummy frame number */
unsigned int dummy_num;
/*! @brief The Dual/Quad spi mode selection.*/
enum { QSPI_ALL, QSPI_DATA_ONLY, QSPI_ADDR_DATA } qspi_mode;
};

struct metal_spi_vtable {
Expand Down
125 changes: 122 additions & 3 deletions src/drivers/sifive_spi0.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,10 +63,16 @@ static int configure_spi(struct __metal_driver_sifive_spi0 *spi,
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_SINGLE;
break;
case METAL_SPI_DUAL:
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_DUAL;
if (config->qspi_mode == QSPI_ALL)
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_DUAL;
else
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_SINGLE;
break;
case METAL_SPI_QUAD:
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_QUAD;
if (config->qspi_mode == QSPI_ALL)
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_QUAD;
else
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_SINGLE;
break;
default:
/* Unsupported value */
Expand Down Expand Up @@ -131,13 +137,36 @@ static int configure_spi(struct __metal_driver_sifive_spi0 *spi,
return 0;
}

static void spi_mode_switch(struct __metal_driver_sifive_spi0 *spi,
struct metal_spi_config *config,
unsigned int qspi_mode) {
long control_base =
__metal_driver_sifive_spi0_control_base((struct metal_spi *)spi);

if (config->qspi_mode == qspi_mode) {
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) &= ~(METAL_SPI_PROTO_MASK);
switch (config->protocol) {
case METAL_SPI_DUAL:
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_DUAL;
break;
case METAL_SPI_QUAD:
METAL_SPI_REGW(METAL_SIFIVE_SPI0_FMT) |= METAL_SPI_PROTO_QUAD;
break;
default:
/* Unsupported value */
return;
}
}
}

int __metal_driver_sifive_spi0_transfer(struct metal_spi *gspi,
struct metal_spi_config *config,
size_t len, char *tx_buf,
char *rx_buf) {
struct __metal_driver_sifive_spi0 *spi = (void *)gspi;
long control_base = __metal_driver_sifive_spi0_control_base(gspi);
int rc = 0;
size_t i = 0;

rc = configure_spi(spi, config);
if (rc != 0) {
Expand All @@ -153,7 +182,97 @@ int __metal_driver_sifive_spi0_transfer(struct metal_spi *gspi,
/* Declare time_t variables to break out of infinite while loop */
time_t endwait;

for (size_t i = 0; i < len; i++) {
for (i = 0; i < config->cmd_num; i++) {

while (METAL_SPI_REGW(METAL_SIFIVE_SPI0_TXDATA) & METAL_SPI_TXDATA_FULL)
;

if (tx_buf) {
METAL_SPI_REGB(METAL_SIFIVE_SPI0_TXDATA) = tx_buf[i];
} else {
METAL_SPI_REGB(METAL_SIFIVE_SPI0_TXDATA) = 0;
}

endwait = metal_time() + METAL_SPI_RXDATA_TIMEOUT;

while ((rxdata = METAL_SPI_REGW(METAL_SIFIVE_SPI0_RXDATA)) &
METAL_SPI_RXDATA_EMPTY) {
if (metal_time() > endwait) {
METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSMODE) &=
~(METAL_SPI_CSMODE_MASK);

return 1;
}
}

if (rx_buf) {
rx_buf[i] = (char)(rxdata & METAL_SPI_TXRXDATA_MASK);
}
}

/* switch to Dual/Quad mode */
spi_mode_switch(spi, config, QSPI_ADDR_DATA);

/* Send Addr data */
for (; i < (config->cmd_num + config->addr_num); i++) {

while (METAL_SPI_REGW(METAL_SIFIVE_SPI0_TXDATA) & METAL_SPI_TXDATA_FULL)
;

if (tx_buf) {
METAL_SPI_REGB(METAL_SIFIVE_SPI0_TXDATA) = tx_buf[i];
} else {
METAL_SPI_REGB(METAL_SIFIVE_SPI0_TXDATA) = 0;
}

endwait = metal_time() + METAL_SPI_RXDATA_TIMEOUT;

while ((rxdata = METAL_SPI_REGW(METAL_SIFIVE_SPI0_RXDATA)) &
METAL_SPI_RXDATA_EMPTY) {
if (metal_time() > endwait) {
METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSMODE) &=
~(METAL_SPI_CSMODE_MASK);

return 1;
}
}

if (rx_buf) {
rx_buf[i] = (char)(rxdata & METAL_SPI_TXRXDATA_MASK);
}
}

/* Send Dummy data */
for (; i < (config->cmd_num + config->addr_num + config->dummy_num); i++) {

while (METAL_SPI_REGW(METAL_SIFIVE_SPI0_TXDATA) & METAL_SPI_TXDATA_FULL)
;

if (tx_buf) {
METAL_SPI_REGB(METAL_SIFIVE_SPI0_TXDATA) = tx_buf[i];
} else {
METAL_SPI_REGB(METAL_SIFIVE_SPI0_TXDATA) = 0;
}

endwait = metal_time() + METAL_SPI_RXDATA_TIMEOUT;

while ((rxdata = METAL_SPI_REGW(METAL_SIFIVE_SPI0_RXDATA)) &
METAL_SPI_RXDATA_EMPTY) {
if (metal_time() > endwait) {
METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSMODE) &=
~(METAL_SPI_CSMODE_MASK);
return 1;
}
}
if (rx_buf) {
rx_buf[i] = (char)(rxdata & METAL_SPI_TXRXDATA_MASK);
}
}

/* switch to Dual/Quad mode */
spi_mode_switch(spi, config, QSPI_DATA_ONLY);

for (; i < len; i++) {
/* Master send bytes to the slave */

/* Wait for TXFIFO to not be full */
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