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Removed unnecessary use of Locks.
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@NandkumarJoshi
NandkumarJoshi committed Aug 27, 2020
1 parent 5546cbc commit e17fa32
Showing 1 changed file with 8 additions and 79 deletions.
87 changes: 8 additions & 79 deletions src/drivers/sifive_ccache0.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,6 @@

#include <metal/drivers/sifive_ccache0.h>
#include <metal/init.h>
#include <metal/io.h>
#include <metal/lock.h>
#include <metal/machine.h>
#include <stdint.h>

Expand All @@ -31,50 +29,28 @@

#define SIFIVE_CCACHE0_WAY_ENABLE_MASK 0x000000FFUL

/* Lock for accessing cache APIs from multiple harts */
METAL_LOCK_DECLARE(sifive_ccache0_lock);

/* Enable locks if multiple harts are present */
#if __METAL_DT_MAX_HARTS > 1
#define SIFIVE_CCACHE0_ACQUIRE_LOCK \
if (metal_lock_take(&sifive_ccache0_lock) == 0) {

#define SIFIVE_CCACHE0_RELEASE_LOCK \
metal_lock_give(&sifive_ccache0_lock); \
}
#else
#define SIFIVE_CCACHE0_ACQUIRE_LOCK
#define SIFIVE_CCACHE0_RELEASE_LOCK
#endif

int sifive_ccache0_interrupts[] = METAL_SIFIVE_CCACHE0_INTERRUPTS;
static int sifive_ccache0_interrupts[] = METAL_SIFIVE_CCACHE0_INTERRUPTS;

/* Initialize cache at start-up via metal constructors */
METAL_CONSTRUCTOR(_sifive_ccache0_init) { sifive_ccache0_init(); }

int sifive_ccache0_init(void) {
int ret = 0;
int ret;

/* Initialize locks to be used later on */
ret = metal_lock_init(&sifive_ccache0_lock);
sifive_ccache0_config config;

if (ret == 0) {
sifive_ccache0_config config;
/* Get cache configuration data */
sifive_ccache0_get_config(&config);

/* Get cache configuration data */
sifive_ccache0_get_config(&config);
/* Enable ways */
ret = sifive_ccache0_set_enabled_ways(config.num_ways);

/* Enable ways */
ret = sifive_ccache0_set_enabled_ways(config.num_ways);
}
return ret;
}

void sifive_ccache0_get_config(sifive_ccache0_config *config) {
uint32_t val;

SIFIVE_CCACHE0_ACQUIRE_LOCK

if (config) /* Check for NULL */
{
val = REGW(METAL_SIFIVE_CCACHE0_CONFIG);
Expand All @@ -88,30 +64,24 @@ void sifive_ccache0_get_config(sifive_ccache0_config *config) {
config->block_size =
2 ^ ((val & SIFIVE_CCACHE0_CONFIG_BLOCKS_MASK) >> REG_SHIFT_24);
}
SIFIVE_CCACHE0_RELEASE_LOCK
}

uint32_t sifive_ccache0_get_enabled_ways(void) {

uint32_t val = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK

val = SIFIVE_CCACHE0_WAY_ENABLE_MASK & REGW(METAL_SIFIVE_CCACHE0_WAYENABLE);

/* The stored number is the way index, so increment by 1 */
val++;

SIFIVE_CCACHE0_RELEASE_LOCK

return val;
}

int sifive_ccache0_set_enabled_ways(uint32_t ways) {

int ret = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK
/* We can't decrease the number of enabled ways */
if (sifive_ccache0_get_enabled_ways() > ways) {
ret = -1;
Expand All @@ -128,22 +98,17 @@ int sifive_ccache0_set_enabled_ways(uint32_t ways) {
}
}

SIFIVE_CCACHE0_RELEASE_LOCK

return ret;
}

void sifive_ccache0_inject_ecc_error(uint32_t bitindex,
sifive_ccache0_ecc_errtype_t type) {
SIFIVE_CCACHE0_ACQUIRE_LOCK
/* Induce ECC error at given bit index and location */
REGW(METAL_SIFIVE_CCACHE0_ECCINJECTERROR) =
(uint32_t)(((type & 0x01) << REG_SHIFT_16) | (bitindex & 0xFF));
SIFIVE_CCACHE0_RELEASE_LOCK
}

void sifive_ccache0_flush(uintptr_t flush_addr) {
SIFIVE_CCACHE0_ACQUIRE_LOCK
/* Block memory access until operation completed */
__asm volatile("fence rw, io" : : : "memory");

Expand All @@ -154,13 +119,11 @@ void sifive_ccache0_flush(uintptr_t flush_addr) {
#endif

__asm volatile("fence io, rw" : : : "memory");
SIFIVE_CCACHE0_RELEASE_LOCK
}

uintptr_t sifive_ccache0_get_ecc_fix_addr(sifive_ccache0_ecc_errtype_t type) {
uintptr_t addr = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK
switch (type) {
/* Get most recently ECC corrected address */
case SIFIVE_CCACHE0_DATA:
Expand All @@ -171,15 +134,13 @@ uintptr_t sifive_ccache0_get_ecc_fix_addr(sifive_ccache0_ecc_errtype_t type) {
addr = (uintptr_t)REGD(METAL_SIFIVE_CCACHE0_DIRECCFIXLOW);
break;
}
SIFIVE_CCACHE0_RELEASE_LOCK

return addr;
}

uint32_t sifive_ccache0_get_ecc_fix_count(sifive_ccache0_ecc_errtype_t type) {
uint32_t count = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK
switch (type) {
/* Get number of times ECC errors were corrected */
case SIFIVE_CCACHE0_DATA:
Expand All @@ -191,14 +152,12 @@ uint32_t sifive_ccache0_get_ecc_fix_count(sifive_ccache0_ecc_errtype_t type) {
break;
}

SIFIVE_CCACHE0_RELEASE_LOCK
return count;
}

uintptr_t sifive_ccache0_get_ecc_fail_addr(sifive_ccache0_ecc_errtype_t type) {
uintptr_t addr = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK
switch (type) {
/* Get address location of most recent uncorrected ECC error */
case SIFIVE_CCACHE0_DATA:
Expand All @@ -210,14 +169,12 @@ uintptr_t sifive_ccache0_get_ecc_fail_addr(sifive_ccache0_ecc_errtype_t type) {
break;
}

SIFIVE_CCACHE0_RELEASE_LOCK
return addr;
}

uint32_t sifive_ccache0_get_ecc_fail_count(sifive_ccache0_ecc_errtype_t type) {
uint32_t count = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK
switch (type) {
/* Get number of times ECC errors were not corrected */
case SIFIVE_CCACHE0_DATA:
Expand All @@ -229,44 +186,33 @@ uint32_t sifive_ccache0_get_ecc_fail_count(sifive_ccache0_ecc_errtype_t type) {
break;
}

SIFIVE_CCACHE0_RELEASE_LOCK
return count;
}

uint64_t sifive_ccache0_get_way_mask(uint32_t master_id) {
uint64_t val = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK

/* Get way mask for given master ID */
val = REGD(METAL_SIFIVE_CCACHE0_WAYMASK0 + master_id * 8);

SIFIVE_CCACHE0_RELEASE_LOCK

return val;
}

int sifive_ccache0_set_way_mask(uint32_t master_id, uint64_t waymask) {
SIFIVE_CCACHE0_ACQUIRE_LOCK

/* Set way mask for given master ID */
REGD(METAL_SIFIVE_CCACHE0_WAYMASK0 + master_id * 8) = waymask;

SIFIVE_CCACHE0_RELEASE_LOCK

return 0;
}

void sifive_ccache0_set_pmevent_selector(uint32_t counter, uint64_t mask) {

#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
SIFIVE_CCACHE0_ACQUIRE_LOCK

/* Set event selector for specified L2 event counter */
REGD(METAL_SIFIVE_CCACHE0_PMEVENTSELECT0 + counter * 8) = mask;

SIFIVE_CCACHE0_RELEASE_LOCK
}
#endif
return;
Expand All @@ -277,11 +223,9 @@ uint64_t sifive_ccache0_get_pmevent_selector(uint32_t counter) {

#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
SIFIVE_CCACHE0_ACQUIRE_LOCK

/* Get event selector for specified L2 event counter */
val = REGD(METAL_SIFIVE_CCACHE0_PMEVENTSELECT0 + counter * 8);

SIFIVE_CCACHE0_RELEASE_LOCK
}
#endif
return val;
Expand All @@ -291,11 +235,8 @@ void sifive_ccache0_clr_pmevent_counter(uint32_t counter) {

#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
SIFIVE_CCACHE0_ACQUIRE_LOCK
/* Clear specified L2 event counter */
REGD(METAL_SIFIVE_CCACHE0_PMEVENTCOUNTER0 + counter * 8) = 0;

SIFIVE_CCACHE0_RELEASE_LOCK
}
#endif
return;
Expand All @@ -312,8 +253,6 @@ uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter) {
/* Set counter register offset */
counter *= 8;

SIFIVE_CCACHE0_ACQUIRE_LOCK

#if __riscv_xlen == 32
do {
vh = REGW(METAL_SIFIVE_CCACHE0_PMEVENTCOUNTER0 + counter + 4);
Expand All @@ -323,8 +262,6 @@ uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter) {
#else
val = REGD(METAL_SIFIVE_CCACHE0_PMEVENTCOUNTER0 + counter);
#endif

SIFIVE_CCACHE0_RELEASE_LOCK
}
#endif
#if __riscv_xlen == 32
Expand All @@ -335,29 +272,21 @@ uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter) {
}

void sifive_ccache0_set_client_filter(uint64_t mask) {
SIFIVE_CCACHE0_ACQUIRE_LOCK

/* Set clients to be excluded from performance monitoring */
REGD(METAL_SIFIVE_CCACHE0_PMCLIENTFILTER) = mask;

SIFIVE_CCACHE0_RELEASE_LOCK
}

uint64_t sifive_ccache0_get_client_filter(void) {
uint64_t val = 0;

SIFIVE_CCACHE0_ACQUIRE_LOCK

/* Get currently active client filter mask */
val = REGD(METAL_SIFIVE_CCACHE0_PMCLIENTFILTER);

SIFIVE_CCACHE0_RELEASE_LOCK

return val;
}

int sifive_ccache0_get_interrupt_id(uint32_t src) {

int ret = 0;

if (src < (uint32_t)sizeof(sifive_ccache0_interrupts) / sizeof(int)) {
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