v1.2

grounded panel
I2C direction (Kasli mode)
DIN compatible with Kasli
fixed silkscreen issues - wrong up/down VHDCI description
added testpoints
fixed panel "poower" typo (issue #4 )
2018.11.28 fixed panel - DC jack hole changed from 8 to 9.4mm

v1.1

swapped some LVDS lines - FMC clock lines on LVDS0
Altium sources are in old repository and in PCB_3U_VHDCI_breakout.7z

v1.0

VHDCI_Carrier/v1.0

v1.2