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Robert Jordens edited this page Oct 26, 2017 · 88 revisions

Urukul DDS extension

Urukul Sketch Rendering

Urukul is a low-cost 4 channel DDS-based frequency synthesiser.

  • Like Mirny Microwave Synthesiser (VCO/PLL-based) but with a DDS as the synthesizer (same RF signal chain minus the frequency double/tripler)
  • For sub-Hz frequency resolution and controlled phase steps (absolute phase control is a goal but not a requirement)
  • External SMA reference frequency input.
  • As many channels as reasonably possible on a 100x160mm Eurocard
  • DDS, e.g. AD9912, AD9910

Current Urukul issues

Specification

  • Power consumption:
  • Min air flow: 50cm/s

OptIclock requirements

  • Frequency:
    • Lowest output frequency: 1 MHz (goal, notify/discuss when not achieved)
    • Highest output frequency (first Nyquist zone): 200 MHz
    • Reference frequency input: 100 MHz (front panel)
    • Frequency resolution: 1 mHz
    • Frequency/phase update rate:
  • Power:
    • Nominal output power 10 dBm (DDS DAC full scale current 20 mA, attenuators open, switches open)
    • Output power range -20 dBm to 10 dBm
    • Attenuator step resolution 0.5 dB
    • Preferably at least 3 dB well resolved (< 0.01 amplitude step) range from the DDS (ASF, FSC, or VVA+DAC)
    • AM stability: 0.1 dB (from Hz to MHz) (goal, notify/discuss when not achieved)
    • AM temperature coefficient: < 0.01 dB/K
    • Power/amplitude update rate:
  • Phase:
    • Phase offset resolution: 14 bit
    • 0,90,180,270 deg phases symmetric to 0.12 mdeg (~LSB of 14 bit POW)
    • AM-to-PM coefficient: 5 deg/dB (desirable goal) over some reasonable range
    • RF switch turn-on transients: 0.1 deg/s during pulses (excluding the first ~µs)
    • Phase noise floor: -100dBc/Hz
    • SFDR: 50 dB
  • Temporal resolution, FTW/POW updates: 100 ns
  • Temporal resolution RF switch: 100 ns
  • Jitter RF switch: 10 ns
  • Some AD9912 measurements: http://www.rubiola.org/pdf-slides/2012C-IFCS-DDS.pdf

Front panel

  • 4xSMA for the RF outputs
  • 1xSMA for the reference frequency input, up to 1 GHz.
  • LEDs, if there is space:
    • the four RF switches' positions
    • four further LEDs controlled by the shift register
    • overtemperature/power good.

DDS requirements

DDS chart

  • Requirements and options:
    • optIclock: 48 bit FTW, >= 400 MHz, desirable: 1 GHz, ASF: AD9910 (if the DRG can be used to extend the FTW), AD9912, AD9956, AD9914
    • Oxford: 32 bit FTW, >= 1 GHz, ASF: AD9910, AD9914
  • The AD9914 is pricey and a power hungry beast (but with lots of features). In power down mode is uses as much as the AD9956 in full power mode. But it does have > 2 GHz, wide ASF and 48 bit FTW. It may be supported as a population alternative on the back side of Urukul.
  • The AD9912 does not have an ASF but a DAC full-scale current register that supports 8-31 mA with 10 bit granularity, i.e. more than 10 dB. That's sufficient as the rest of the dynamic range can be handled by the digital attenuator. Since the register is not double-buffered and not synchronized via IO_UPDATE only the low 8 bits can be adjusted in a "clean" fashion. #205.
  • Using the digital ramp generator in the AD9910, the FTW can be extended. Discussion and test in #210. With a strictly power-of-two ramp step, smaller than 2*pi/256 phase steps, and DRG step interval counter values from 1*4 ns to 0xffff*4ns, that will allow for a 7 µHz resolution everywhere below the 0.2 Hz basic 32 bit FTW resolution. In that mode, the explicit control over the phase offset using the register is inoperative.
  • There appear to be potential workarounds for both cases: construct an ASF using the DAC FSC in the AD9912, and using the DRG to extend the FTW in the AD9910. Urukul will be built for both chips.
  • OSK, the profile pins, DRCTL, DRHOLD for the AD9910 should be supported. There are no wires on the EEM connectors but even exposing them via the hardware shift registers is beneficial.

Clock/phases

Clock (DDS REFCLK, 10 MHz-1 GHz) should be able to come from the front panel SMA, or from a coax connector on the board (from the Kasli fan-out internal to the rack), or from a crystal XO on the board. The selection can be done using a solder bridge.

REFCLK should be distributed with a delay-matched fan-out to DDS0:REF_CLK-DDS3:REF_CLK. IO_UPDATE should also be delay-matched.

Synchronization

Some thought should go into synchronizing at least the four DDS chips on one Urukul, if not the DDS chips w.r.t. DRTIO reference clock/time.

Urukul will have deterministic phase control in the sense that phase jumps are well defined and deterministic.

There may be two non-deterministic features (a) the absolute phase and (b) the absolute timing of phase/frequency jumps (both w.r.t. to the reference clock/RTIO TSC/other DDS channels) will non-deterministic across power cycles. For the AD9912 there are four different possible values.

For the AD9912 we will implement this mechanism to reset the internal SYNC_CLK dividers w.r.t. RTIO. The RESET should be gated by SW0-3 and thus be per DDS.

for the AD9910 implement the multichip clock synchronization scheme from AD9910 Figure 53: delay-matched fan-out, e.g. CDCLVC1106, from "EEMA:SYNC_OUT or DDS0:SYNC_OUT0" (solder bridge selectable) to DDS0:SYNC_IN-DDS3:SYNC_IN and EEMB:SYNC_IN. Provide test-points or shift register monitoring for SYNC_SMP_ERR. #213

RF switches

  • One LVDS line on EEMB per RF switch with defined state when no EEMB is plugged in
  • XORs the SW0-3 with the corresponding shift register outputs to control the RF switches

EEM connector usage

We envisage two ways of controlling Urukul from Kasli: the "compact" (basic) method (a) and the "high-bandwidth" method (b). Selection is a DIP switch.

Also for the (a) method we have to distinguish the AD9912 which can only be synchronized using its master reset (DDS_RESET) and the AD9910 which is synchronized using SYNC_IN pulses.

IDC (a) AD9912 (a) AD9910 (b) AD9910
A0 CLK CLK CLK
A1 MOSI MOSI MOSI
A2 MISO MISO NU_CLK
A3 CS0 CS0 CS0
A4 CS1 CS1 CS1
A5 CS2 CS2 NU_CS
A6 IO_UPDATE IO_UPDATE IO_UPDATE
A7 DDS_RESET SYNC_OUT SYNC_OUT
B0 (SYNC_CLK) NU_MOSI0
B1 (SYNC_IN) NU_MOSI1
B2 (IO_UPDATE_RET) (IO_UPDATE_RET) NU_MOSI2
B3 NU_MOSI3
B4 SW0 SW0 SW0
B5 SW1 SW1 SW1
B6 SW2 SW2 SW2
B7 SW3 SW3 SW3

Signals in parenthesis should be scrapped after the first prototype round if they are not needed.

(a) Default operation

Operates from 1 or 2 EEM connectors (IDC) using standard Kasli gateware, with all DDSs sharing a single SPI bus. The RF switches may be controlled either from this bus for single EEM operation, or from dedicated LVDS lines on the second (optional) EEM for best timing resolution. The second EEM

EEMA

Single SPI bus providing control of all 4 DDSs, attenuators (daisy chained) and RF switches (shift registers).

Also lines for synchronization (SYNC_OUT to DDS0-3 for AD9910, DDS_RESET for AD9912) and IO_UPDATE.

CS decoder assignment (this assumes that chips are not bothered by glitches on the CS line):

  1. None (also activated by CS0-2 pull downs/defined state of the LVDS lines)
  2. SR 16 bits (write: 4x RF switch SW0-3 XOR with B4-B7, 4x red LED OR with error, 3 PROFILE[2:0], ATT_LE, CLK_SEL, SYNC_SEL, RST, IO_RST; read: 4x RF_SW, 4x SMP_ERR, 4x PLL_LOCK, 4x IFC_MODE)
  3. ATT0-3 (4x8=32 bit daisy chain)
  4. DDS0-3 in parallel
  5. DDS0
  6. DDS1
  7. DDS2
  8. DDS3

EEMB

  • SYNC_CLK0 from DDS0 (on a clock-capable Kasli pin)
  • SYNC_IN from DDS0
  • Return for IO_UPDATE RTT measurement
  • SW[3:0]

(b) NU-Servo (Wide DDS IO bandwidth)

Requires 2 IDCs and custom gateware, such as the proposed servo (see below). Allows all DDSs to be programmed simultaneously via a quad SPI bus for maximum update rate, and provides high timing resolution control of the RF switches.

Normal SPI bus

Single width SPI bus with decoded CS1,CS0 to control the shift register. No MISO. No register readback no DRG monitoring, no PLL monitoring.

CS encoding:

  1. None
  2. SR 16 (switches, leds, status etc)
  3. ATT
  4. DDS3:0 all parallel for configuration, overriding the quad SPI interface the quad SPI interface needs to be silent, NU_CS deasserted

Quad SPI bus

Quad SPI bus providing control of all 4 DDSs. The four DDS SDI are connected to the four MOSI lines. Single CS. No MISO.

Novo to Urukul servo

See NovoUrukulServo.

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