Urukul
Urukul is a 4 channel DDS-based frequency synthesizer for the EEM form factor. It provides sub-Hz frequency resolution, controlled phase steps, and accurate output amplitude control.
- Two variants of Urukul are available with different DDS chips: AD9912 and AD9910
- Output frequency (-3 dB): 1 - 460 MHz (TBC)
- Frequency resolution: ~4 µHz (48 bit, AD9912), ~0.25 Hz (32 bit, AD9910, but see also #210 for an extension of the frequency resolution using the DRG)
- Frequency update rate using the single-width SPI bus: > 500 kHz burst aggregate, TBC
- Phase offset resolution: 14 bit (AD9912), 16 bit (AD9910)
- Digital amplitude (ASF) resolution: 14 bit (AD9910 only)
- DAC full scale current resolution: 10 bit (AD9912), 8 bit (AD9910)
- DAC full scale current slew rate: ~6 mA/20 µs, 100 ns/LSB (AD9912) #205
- Temporal resolution, FTW/POW/ASF updates: 4 ns (IO_UPDATE on a SERDES TTLOut) (TBC)
- OSK: not supported
- DRG control pins: not supported
- Profile (using the AD9910 PROFILE pins): ganged and exposed in the shift register
- Anti-Aliasing: The lowpass can be replaced by a custom discrete filter. This allows usage of the second or third Nyquist zones.
- Digital step attenuator resolution: 0.5 dB
- Digital step attenuator range: 0 to -31.5 dB
- Nominal max output power (1dB compression from expected attenuator/ASF/FSC setting due to pre-amplifier): 10 dBm
- Temporal resolution RF switch: 1 ns (limited by FPGA OSERDES/ARTIQ TTLOut resolution)
- Jitter RF switch: < 1 ns, TBC
- RF switches controlled by dedicated LVDS lines on EEM1 and by shift register (logical OR)
- Phase noise/stability: TBD
- Phase noise floor: < -100dBc/Hz (TBC)
- SFDR: > 50 dB (TBC)
- AM-to-PM coefficient: < 5 deg/dB (TBC)
- Amplitude temperature coefficient: < 0.01 dB/K TBC
- Amplitude noise/stability: TBD
- RF switch turn-on chirp: <0.1 deg/s (excluding the first ~µs)
- Input frequency: 10 MHz to 1 GHz (TBC, depending on PLL/clocking configuration)
- Input power: 10 dBm nominal (TBD to TBD dBm)
- Source: External SMA, internal MMCX (from Kasli or Clocker), or on-board XO
- Selection between MMCX and XO: on board jumpers
- Selection between MMCX/XO and SMA: software
- Default design is 1 GHz DDS clock from 125 MHz or 100 MHz reference frequency input using the DDS PLLs
- Air flow: > 50cm/s (from thermal simulation, #321), TBD
- Power consumption: ~10 W (from design estimate), TBD
- Each channel:
- SMA RF output
- Green LED indicating RF output enabled
- Red LED indicating DDS sychronization/PLL error or software-controlled function
- One SMA for the reference frequency input, up to 1 GHz
- Red LED: over temperature
- Green LED: power good
Urukul has deterministic phase control in the sense that phase jumps are well defined and deterministic in their jump size.
Phase control beyond that level requires aligning the synchronization clock phase to the other DDSs on a card and more importantly to the RTIO timebase.
Different strategies will be evaluated:
DDS_RESET provides a way to deterministically reset all AD9912 DDS SYNC_CLK dividers (see a corresponding ADI discussion). It remains to be seen whether this also works when using the PLL. If it does not, the AD9912 variant can only made absolutely synchronous when not using the PLL.
DDS_RESET needs to be well timed w.r.t. DDS SYSCLK (meet S/H). That requires determination of the timing t_RESET of DDS_RESET w.r.t. DDS REFCLK/SYSCLK. This which will need to be measured manually, computed using cable lengths and empirical offsets, or always found empirically using a measurement of phase update determinism when scanning a delay. From the timing t_RESET the proper timing t_UPDATE or IO_UPDATE w.r.t. SYNCCLK can be inferred. The latter should only be required once for a given hardware design.
Using the AD9910 SYNC circuitry, a marker signal (SYNC) is distributed to all DDS that resets their SYNCCLK dividers. If SYNC originates from the FPGA (Kasli/Sayma/Metlino), then the delay of SYNC_OUT w.r.t. REFCLK/SYSCLK needs to be reproducibly adjusted. This is done using the DDS-internal delays seeded with a persistently stored initial value (start with last value, optimize it, and store it for next optimization after reboot).
Given this synchronization the proper timing t_UPDATE or IO_UPDATE w.r.t. SYNCCLK can be inferred. The latter should only be required once for a given hardware design.
In this mode SYNC would be driven by the first DDS and emitted from Urukul to the FPGA. On the FPGA it would be used to re-time IO_UPDATE (or PROFILE) with respect to SYNC CLK and thus SYSCLK. The requirement on reproducibly adjusting the latency (from RTIO clock to DDS/SYNC domain) are similar to AD9910 active SYNC with the exception that the FPGA needs to perform delay adjustment as well now.
This mode does not place the IO_UPDATE timing reproducibly w.r.t. RTIO clock. It only ensures that IO_UPDATE/PROFILE always meets S/H w.r.t. DDS SYNCCLK.
The IO and logic router on Urukul controls the SPI buses, multiplexes the different chips, and implements the shift register for control of miscellaneous functionality.
Its implementation and functionality are documented in the CPLD source code.
Urukul can be integrated with Novo to form a multi-channel, multi-profile digital servo controller. See NovoUrukulServo for details.
