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applying EMACS vhdl-beautify-buffer & update-sensitivity-list-buffer
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@ruck314
ruck314 committed Jul 6, 2024
1 parent f7e4ea0 commit 21c6d32
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Showing 2 changed files with 58 additions and 58 deletions.
32 changes: 16 additions & 16 deletions protocol/gpuAsync/rtl/AxiPcieGpuAsyncControl.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -54,10 +54,10 @@ entity AxiPcieGpuAsyncControl is
dynamicRouteMasks : out slv(7 downto 0);
dynamicRouteDests : out slv(7 downto 0);
-- DMA Write Engine
dmaWrDescReq : in AxiWriteDmaDescReqType;
dmaWrDescAck : out AxiWriteDmaDescAckType;
dmaWrDescRet : in AxiWriteDmaDescRetType;
dmaWrDescRetAck : out sl;
dmaWrDescReq : in AxiWriteDmaDescReqType;
dmaWrDescAck : out AxiWriteDmaDescAckType;
dmaWrDescRet : in AxiWriteDmaDescRetType;
dmaWrDescRetAck : out sl;

-- DMA Read Engine
dmaRdDescReq : out AxiReadDmaDescReqType;
Expand Down Expand Up @@ -265,7 +265,7 @@ begin
for i in 0 to MAX_BUFFERS_G-1 loop
axiSlaveRegister (axilEp, toSlv(256+i*16+0, 12), 0, v.remoteWriteAddrL(i)); -- 0x1x0 (x = 0,1,2,3....)
axiSlaveRegister (axilEp, toSlv(256+i*16+4, 12), 0, v.remoteWriteAddrH(i)); -- 0x1x4 (x = 0,1,2,3....)
axiSlaveRegister (axilEp, toSlv(256+i*16+8, 12), 0, v.remoteWriteSize(i)); -- 0x1x8 (x = 0,1,2,3....)
axiSlaveRegister (axilEp, toSlv(256+i*16+8, 12), 0, v.remoteWriteSize(i)); -- 0x1x8 (x = 0,1,2,3....)
end loop;

for i in 0 to MAX_BUFFERS_G-1 loop
Expand Down Expand Up @@ -306,9 +306,9 @@ begin

v.dmaWrDescAck.buffId(3 downto 0) := r.nextWriteIdx;

v.dmaWrDescAck.metaAddr(31 downto 0) := r.remoteWriteAddrL(conv_integer(r.nextWriteIdx));
v.dmaWrDescAck.metaAddr(31 downto 0) := r.remoteWriteAddrL(conv_integer(r.nextWriteIdx));
v.dmaWrDescAck.metaAddr(63 downto 32) := r.remoteWriteAddrH(conv_integer(r.nextWriteIdx));
v.dmaWrDescAck.address(31 downto 0) := r.remoteWriteAddrL(conv_integer(r.nextWriteIdx)) + DMA_AXI_CONFIG_G.DATA_BYTES_C;
v.dmaWrDescAck.address(31 downto 0) := r.remoteWriteAddrL(conv_integer(r.nextWriteIdx)) + DMA_AXI_CONFIG_G.DATA_BYTES_C;
v.dmaWrDescAck.address(63 downto 32) := r.remoteWriteAddrH(conv_integer(r.nextWriteIdx));

if r.remoteWriteEn(conv_integer(r.nextWriteIdx)) = '1' or r.writeEnable = '0' then
Expand Down Expand Up @@ -387,7 +387,7 @@ begin
v.dmaRdDescReq.id := (others => '0');
v.dmaRdDescReq.dest := (others => '0');

v.dmaRdDescReq.address(31 downto 0) := r.remoteReadAddrL(conv_integer(r.nextReadIdx));
v.dmaRdDescReq.address(31 downto 0) := r.remoteReadAddrL(conv_integer(r.nextReadIdx));
v.dmaRdDescReq.address(63 downto 32) := r.remoteReadAddrH(conv_integer(r.nextReadIdx));

v.txState := MOVE_S;
Expand Down Expand Up @@ -415,14 +415,14 @@ begin

--------------------------------------------------------------------------------------------
-- Outputs
awCache <= r.awCache;
arCache <= r.arCache;
writeSlave <= r.writeSlave;
readSlave <= r.readSlave;
dmaWrDescAck <= r.dmaWrDescAck;
dmaWrDescRetAck <= r.dmaWrDescRetAck;
dmaRdDescReq <= r.dmaRdDescReq;
dmaRdDescRetAck <= r.dmaRdDescRetAck;
awCache <= r.awCache;
arCache <= r.arCache;
writeSlave <= r.writeSlave;
readSlave <= r.readSlave;
dmaWrDescAck <= r.dmaWrDescAck;
dmaWrDescRetAck <= r.dmaWrDescRetAck;
dmaRdDescReq <= r.dmaRdDescReq;
dmaRdDescRetAck <= r.dmaRdDescRetAck;
dynamicRouteMasks <= r.dynamicRouteMasks;
dynamicRouteDests <= r.dynamicRouteDests;

Expand Down
84 changes: 42 additions & 42 deletions protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ use axi_pcie_core.AxiPciePkg.all;

entity AxiPcieGpuAsyncCore is
generic (
TPD_G : time := 1 ns;
TPD_G : time := 1 ns;
NUM_CHAN_G : positive range 1 to 4 := 1;
DMA_AXIS_CONFIG_G : AxiStreamConfigType);
port (
Expand All @@ -51,8 +51,8 @@ entity AxiPcieGpuAsyncCore is
mAxisMaster : out AxiStreamMasterType;
mAxisSlave : in AxiStreamSlaveType;
-- AXI Stream Interface bypass (axisClk domain)
bypassMaster : out AxiStreamMasterType;
bypassSlave : in AxiStreamSlaveType;
bypassMaster : out AxiStreamMasterType;
bypassSlave : in AxiStreamSlaveType;
-- AXI4 Interfaces (axiClk domain)
axiClk : in sl;
axiRst : in sl;
Expand All @@ -74,33 +74,33 @@ architecture mapping of AxiPcieGpuAsyncCore is
TUSER_BITS_C => 8,
TUSER_MODE_C => TUSER_FIRST_LAST_C);

signal dmaWrDescReq : AxiWriteDmaDescReqType;
signal dmaWrDescAck : AxiWriteDmaDescAckType;
signal dmaWrDescRet : AxiWriteDmaDescRetType;
signal dmaWrDescRetAck : sl;
signal dmaWrDescReq : AxiWriteDmaDescReqType;
signal dmaWrDescAck : AxiWriteDmaDescAckType;
signal dmaWrDescRet : AxiWriteDmaDescRetType;
signal dmaWrDescRetAck : sl;

signal dmaRdDescReq : AxiReadDmaDescReqType;
signal dmaRdDescAck : sl;
signal dmaRdDescRet : AxiReadDmaDescRetType;
signal dmaRdDescRetAck : sl;
signal dmaRdDescReq : AxiReadDmaDescReqType;
signal dmaRdDescAck : sl;
signal dmaRdDescRet : AxiReadDmaDescRetType;
signal dmaRdDescRetAck : sl;

signal dynamicRouteMasks : slv(7 downto 0);
signal dynamicRouteDests : slv(7 downto 0);
signal mAxisDemuxMasters : AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0);
signal mAxisDemuxSlaves : AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0);
signal mAxisDemuxMasters : AxiStreamMasterArray(1 downto 0);
signal mAxisDemuxSlaves : AxiStreamMasterArray(1 downto 0);

signal awCache : slv(3 downto 0);
signal arCache : slv(3 downto 0);
signal awCache : slv(3 downto 0);
signal arCache : slv(3 downto 0);

signal sAxisMasterInt : AxiStreamMasterType;
signal sAxisSlaveInt : AxiStreamSlaveType;
signal mAxisMasterInt : AxiStreamMasterType;
signal mAxisSlaveInt : AxiStreamSlaveType;
signal sAxisMasterInt : AxiStreamMasterType;
signal sAxisSlaveInt : AxiStreamSlaveType;
signal mAxisMasterInt : AxiStreamMasterType;
signal mAxisSlaveInt : AxiStreamSlaveType;

begin

-- direct connection to Pcie core from Demux
bypassMaster <= mAxisDemuxMasters(1);
bypassMaster <= mAxisDemuxMasters(1);
mAxisDemuxSlaves(1) <= bypassSlave;
------------------------------
-- AXI-Lite Control/Monitoring
Expand Down Expand Up @@ -134,21 +134,21 @@ begin
-- AXI-Stream Demux
------------------------------
AxiStreamDeMux_inst : entity surf.AxiStreamDeMux
generic map (
TPD_G => TPD_G,
NUM_MASTERS_G => 2,
MODE_G => "DYNAMIC")
port map (
axisClk => axisClk,
axisRst => axisRst,
dynamicRouteMasks => dynamicRouteMasks,
dynamicRouteDests => dynamicRouteDests,
sAxisMaster => sAxisMaster,
sAxisSlave => sAxisSlave,
mAxisMasters => mAxisDemuxMasters,
mAxisSlaves => mAxisDemuxSlaves
);
generic map (
TPD_G => TPD_G,
NUM_MASTERS_G => 2,
MODE_G => "DYNAMIC")
port map (
axisClk => axisClk,
axisRst => axisRst,
dynamicRouteMasks => dynamicRouteMasks,
dynamicRouteDests => dynamicRouteDests,
sAxisMaster => sAxisMaster,
sAxisSlave => sAxisSlave,
mAxisMasters => mAxisDemuxMasters,
mAxisSlaves => mAxisDemuxSlaves
);

------------------------------------
-- Stream receiver to GPU DMA
------------------------------------
Expand All @@ -173,12 +173,12 @@ begin
mAxisMaster => sAxisMasterInt,
mAxisSlave => sAxisSlaveInt);

U_DmaWrite: entity surf.AxiStreamDmaV2Write
U_DmaWrite : entity surf.AxiStreamDmaV2Write
generic map (
TPD_G => TPD_G,
AXI_READY_EN_G => true,
AXIS_CONFIG_G => PCIE_AXIS_CONFIG_C,
AXI_CONFIG_G => AXI_PCIE_CONFIG_C)
TPD_G => TPD_G,
AXI_READY_EN_G => true,
AXIS_CONFIG_G => PCIE_AXIS_CONFIG_C,
AXI_CONFIG_G => AXI_PCIE_CONFIG_C)
port map (
axiClk => axiClk,
axiRst => axiRst,
Expand All @@ -196,7 +196,7 @@ begin
-- Stream transmitter from GPU DMA
------------------------------------

U_DmaRead: entity surf.AxiStreamDmaV2Read
U_DmaRead : entity surf.AxiStreamDmaV2Read
generic map (
TPD_G => TPD_G,
AXIS_READY_EN_G => true,
Expand Down Expand Up @@ -235,6 +235,6 @@ begin
mAxisRst => axisRst,
mAxisMaster => mAxisMaster,
mAxisSlave => mAxisSlave);

end mapping;

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