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gpuasynccore.py bug fixes
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mmishra9 committed Jul 8, 2024
1 parent df51c90 commit a969cdb
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -86,8 +86,8 @@ architecture mapping of AxiPcieGpuAsyncCore is

signal dynamicRouteMasks : slv(7 downto 0);
signal dynamicRouteDests : slv(7 downto 0);
signal mAxisDemuxMasters : AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0);
signal mAxisDemuxSlaves : AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0);
signal mAxisDemuxMasters : AxiStreamMasterArray(1 downto 0);
signal mAxisDemuxSlaves : AxiStreamMasterArray(1 downto 0);

signal awCache : slv(3 downto 0);
signal arCache : slv(3 downto 0);
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