Release Candidate v3.8.1

LCLS-II/core/rtl/TPGPkg.vhd

@@ -241,10 +241,11 @@ package TPGPkg is
       -- AC sync from analog or digital AMC
       acMaster           : sl;
       -- Analog lookahead (master) or digital delay (us)
-      acDelay            : slv(14 downto 0);
+      acTS1              : slv(1 downto 0);
+      acPolarity         : sl;
+      acDelay            : slv(12 downto 0);
       inpDelay           : slv(8 downto 0);
       inpDelayLd         : sl;
-      frameDelay         : slv(15 downto 0);
       baseDivisor        : slv(15 downto 0);
       pulseId            : slv(63 downto 0);
       pulseIdWrEn        : sl;
@@ -293,11 +294,12 @@ package TPGPkg is
       txPolarity         => '0',
       baseDivisor        => x"00C8",
       acMaster           => '1',
-      acDelay            => toSlv(100, 15),
+      acTS1              => "00",
+      acPolarity         => '0',
+      acDelay            => toSlv(100, 13),
       --    acDelay           => toSlv(733,15),
       inpDelay           => (others => '0'),
       inpDelayLd         => '0',
-      frameDelay         => x"0000",
       pulseId            => (others => '0'),
       pulseIdWrEn        => '1',
       timeStamp          => (others => '0'),

LCLS-II/core/rtl/TimingDeserializer.vhd

@@ -79,9 +79,9 @@ architecture TimingDeserializer of TimingDeserializer is
   signal r   : RegType := REG_INIT_C;
   signal rin : RegType;
   signal crc : slv(31 downto 0);
-   
+
 begin
-  
+
   fiducial <= r.fiducial;
   streams  <= r.streams;
   advance  <= r.advance;

LCLS-II/core/rtl/TimingFrameRx.vhd

@@ -83,7 +83,7 @@ architecture rtl of TimingFrameRx is
    signal dframe  : DataArray;
    signal dstrobe : slv(15 downto 1);
    signal dvalid  : slv(15 downto 1);
-   
+
 begin
 
    delayRst <= rxRst or messageDelayRst or doverflow0;

LCLS-II/core/rtl/TimingRx.vhd

@@ -193,7 +193,7 @@ begin
             rxVersion           => rxVersion(1),
             staData             => staData (1));
    end generate;
-    
+
    axilComb : process (axilR, axilRst, axilReadMaster, axilRxLinkUp, axilStatusCounters12,
                        axilStatusCounters3, axilVersion, axilVsnErr, axilWriteMaster, rxStatusCount,
                        timingTSEvCntGray_o, txClkCntS) is

LCLS-II/core/rtl/TimingStreamTx.vhd

@@ -84,10 +84,17 @@ begin
       v := r;
 
       v.dataBuffEn := not r.dataBuffEn;
-      v.dbufData   := D_215_C;
-      v.ecodData   := K_COM_C;
-      v.dataK      := "01";
 
+      if r.dataBuffEn = '1' then
+        v.dbufData   := x"00";
+        v.ecodData   := x"00";
+        v.dataK      := "00";
+      else
+        v.dbufData   := x"00";
+        v.ecodData   := K_COM_C;
+        v.dataK      := "01";
+      end if;
+
       case (r.state) is
         when IDLE_S =>
           v.wordCount := (others=>'0');
@@ -97,42 +104,43 @@ begin
             v.dataBuffEn := '0';
             v.pulseId    := pulseId;
             v.eventCodes := eventCodes;
-            v.dataK      := "11";
+            v.dataK(1)   := '1';
             v.dbufData   := K_280_C;
           end if;
         when FRAME_S =>
           if r.wordCount=NDATABUFF_WORDS then
             v.state     := PULSEID_S;
             v.wordCount := (others=>'0');
-            v.dataK      := "11";
+            v.dataK(1)  := '1';
             v.dbufData   := K_281_C;
           elsif r.dataBuffEn='1' then
             v.dbufData  := r.dataBuff(7 downto 0);
             v.dataBuff  := x"00" & r.dataBuff(r.dataBuff'left downto 8);
             v.wordCount := r.wordCount+1;
           end if;
         when PULSEID_S =>
-          v.dataK     := "00";
-          if r.wordCount=toSlv(32,r.wordCount'length) then
-            v.state     := ECODE_S;
-            v.wordCount := (others=>'0');
-            v.ecodData  := x"7D";
-          else
-            v.wordCount := r.wordCount+1;
-            v.pulseId   := r.pulseId(30 downto 0) & '0';
-            if r.pulseId(31)='0' then
-              v.ecodData := x"70";
+          if r.dataBuffEn='1' then
+            if r.wordCount=toSlv(32,r.wordCount'length) then
+              v.state     := ECODE_S;
+              v.wordCount := (others=>'0');
+              v.ecodData  := x"7D";
             else
-              v.ecodData := x"71";
+              v.wordCount := r.wordCount+1;
+              v.pulseId   := r.pulseId(30 downto 0) & '0';
+              if r.pulseId(31)='0' then
+                v.ecodData := x"70";
+              else
+                v.ecodData := x"71";
+              end if;
             end if;
           end if;
         when ECODE_S =>
           if r.wordCount = toSlv(255,r.wordCount'length) then
             v.state := IDLE_S;
-          else
+          elsif r.dataBuffEn = '1' then
             v.wordCount := r.wordCount+1;
             if r.eventCodes(conv_integer(r.wordCount))='1' then
-              v.dataK    := "00";
+              v.dataK(0) := '0';
               v.ecodData := r.wordCount;
             end if;
           end if;

LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd

@@ -81,7 +81,7 @@ entity TimingGthCoreWrapper is
       txOutClk       : out sl;
 
       loopback : in slv(2 downto 0));
-   
+
 end entity TimingGthCoreWrapper;
 
 architecture rtl of TimingGthCoreWrapper is

conda-recipe/build.sh

@@ -1,4 +1,4 @@
 #!/usr/bin/bash
-  
+
 python setup.py install
 

generateDocumentationAndDeploy.sh

@@ -88,7 +88,7 @@ echo "" > .nojekyll
 echo 'Generating Doxygen code documentation...'
 doxygen -v
 
-# Update the INPUT configuration 
+# Update the INPUT configuration
 echo "INPUT = $TRAVIS_BUILD_DIR" >> $DOXYFILE
 
 # # Update the EXCLUDE configuration