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[202012] [Profile separation] MMU infrastructure update for TD2 (#12739)
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Signed-off-by: Neetha John <nejo@microsoft.com>

This is to backport #12626

Why I did it
There is a need to have separate profiles on compute and storage and this infra update will help achieve that

How I did it
Moved buffer pool/profile and qos definitions on TD2 to a common folder and all TD2 hwsku's will reference that folder
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@neethajohn
neethajohn authored Nov 29, 2022
1 parent 3c88bee commit bbcad13
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1 change: 1 addition & 0 deletions device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/BALANCED
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../../../common/profiles/td2/gen/BALANCED
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6 changes: 6 additions & 0 deletions device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffer_ports_t0.j2
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{% for port_idx in range(0,32) %}
{% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %}
{% endfor %}
{%- endmacro %}
6 changes: 6 additions & 0 deletions device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffer_ports_t1.j2
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{% for port_idx in range(0,32) %}
{% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %}
{% endfor %}
{%- endmacro %}
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BALANCED/buffers_defaults_t0.j2
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1 change: 1 addition & 0 deletions device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/TCP-CENTRIC
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10 changes: 10 additions & 0 deletions device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffer_ports_t0.j2
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{% if PORT_ALL.append("Ethernet0") %}{% endif %}
{% if PORT_ALL.append("Ethernet1") %}{% endif %}
{% if PORT_ALL.append("Ethernet2") %}{% endif %}
{% if PORT_ALL.append("Ethernet3") %}{% endif %}
{% for port_idx in range(1,32) %}
{% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %}
{% endfor %}
{%- endmacro %}
10 changes: 10 additions & 0 deletions device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffer_ports_t1.j2
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{% if PORT_ALL.append("Ethernet0") %}{% endif %}
{% if PORT_ALL.append("Ethernet1") %}{% endif %}
{% if PORT_ALL.append("Ethernet2") %}{% endif %}
{% if PORT_ALL.append("Ethernet3") %}{% endif %}
{% for port_idx in range(1,32) %}
{% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %}
{% endfor %}
{%- endmacro %}
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../../../common/profiles/td2/gen/RDMA-CENTRIC
1 change: 1 addition & 0 deletions device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/TCP-CENTRIC
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../../../common/profiles/td2/gen/TCP-CENTRIC
6 changes: 6 additions & 0 deletions device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffer_ports_t0.j2
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{% for port_idx in range(0,32) %}
{% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %}
{% endfor %}
{%- endmacro %}
6 changes: 6 additions & 0 deletions device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffer_ports_t1.j2
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Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{% for port_idx in range(0,32) %}
{% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %}
{% endfor %}
{%- endmacro %}
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