Support for minigraph generation for packet based chassis. #4479

abdosi · 2021-10-13T14:26:24Z

What I did:

Below changes goes with the sonic-buildimage PR: sonic-net/sonic-buildimage#8966

1. Changes for Generation LC-Graph for packet-based chassis.
2. Added Support Ipv6 Peering on Loopback4096 for voq also
3. Updated asic topology yml files to be offset of slot
4. Made slot_num to take string slot<number> instead of number
5. Consolidated template_dpg_voq_asic.j2 into dpg_asic.j2
6. Remove Loopback4096 from asic topology and parse as dut invertory for
   multi-asic
7. Updated topo_facts parsing for asic topology_
8. Internal BGP Session rename from <VoqChassisInternal> to <ChassisInternal> and take switch_type as value.

How I Verify

Verified gen-mg for multi-asic/voq-chassis/packet-chassis dut's.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>

2. Added Support Ipv6 Peering on Loopback4096 for voq also 3. Updated asic topology yml files to be offset of slot 4. Made slot_num to take string slot<number> instead of number 5. Consolidated template_dpg_voq_asic.j2 into dpg_asic.j2 6. Remove Loopback4096 from asic topology and parse as dut invertory for multi-asic 7. Updated topo_facts parsing for asic topology Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>

abdosi · 2021-10-13T14:42:42Z

cc @sanmalho-git please review.

sanmalho-git · 2021-10-13T18:31:17Z

ansible/lab

+sonic_msft_sup:
+ vars:
+ HwSku: msft-RP-O
+ slot_num: slot0


There are some dependencies on slot_num that I believe are expecting this host variable to be int.

Have fixed in latest commit to strip "slot" from the string.

sanmalho-git · 2021-10-15T15:47:20Z

ansible/library/port_alias.py

 portconfig = os.path.join(FILE_PATH, platform, self.hwsku, str(asic_id), PORTMAP_FILE)
+ else:
+ portconfig = os.path.join(FILE_PATH, platform, self.hwsku, str(slotid), str(asic_id), PORTMAP_FILE)


Is the port_config.ini file different for a card with the same hwsku being in a different slot?

yes, Backend connectivity can be different based on slot the card is inserted.

sanmalho-git · 2021-10-15T18:57:14Z

ansible/templates/minigraph_cpg.j2

+ <Multihop>1</Multihop>
+ <HoldTime>0</HoldTime>
+ <KeepAliveTime>0</KeepAliveTime>
+ <ChassisInternal>{{ switch_type }}</ChassisInternal>


As mentioned in the review in chassis subgroup - we are currently not creating v6 iBGP neighbors across the asics - only v4. The IPv6 routes are carried over the v4 iBGP peer itself.

thanks. for now we want to do Ipv6 peering.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>

abdosi · 2021-10-16T00:58:50Z

@arlakshm can you review/approve this.

What is the motivation for this PR? The minigraph template changes for chassis PR: #4479 removed Bandwidth element with the assumption that interface speed should be configured from port_config. But that will not be the case for multi-asic platform. Due to this change, internal interfaces in multi-asic were coming up without speed configured. How did you do it? Add default interface speed in minigraph png template. How did you verify/test it? Bring up mutli-asic VS and verify that internal interfaces are coming up with default speed and internal BGP sessions are coming up.

sanmalho-git · 2021-11-04T22:38:41Z

@abdosi - sorry, but am just getting to test this PR out on Nokia's VoQ chassis.

I see two issues in the minigraph generated with this PR:

In Cpg
- Missing BGPRouterDeclaration section for remote asics - <remote_linecard>-ASIC<#>
- For multi-asic linecard, missing BGPRouterDeclaraion section for my asics - ASIC<#>
In Dpg, we are missing the DeviceDataPlaneInfo for my asics in a multi-asic linecard
- This is generated in template_dpg_asic, which is dependent on asic_topo_config. For voq_chassis, asic_topo_config is empty dictionary - as the iBGP connections depend on the what linecards are present in the chassis, and also what asics are on each linecard. This was the reason that I had created a seperate minigraph_dpg_voq template.

abdosi · 2021-11-10T23:50:15Z

@abdosi - sorry, but am just getting to test this PR out on Nokia's VoQ chassis.

I see two issues in the minigraph generated with this PR:

In Cpg

Missing BGPRouterDeclaration section for remote asics - <remote_linecard>-ASIC<#>

For multi-asic linecard, missing BGPRouterDeclaraion section for my asics - ASIC<#>

In Dpg, we are missing the DeviceDataPlaneInfo for my asics in a multi-asic linecard

This is generated in template_dpg_asic, which is dependent on asic_topo_config. For voq_chassis, asic_topo_config is empty dictionary - as the iBGP connections depend on the what linecards are present in the chassis, and also what asics are on each linecard. This was the reason that I had created a seperate minigraph_dpg_voq template.

@sanmalho-git thanks for validating. we will check and fix this by this week.

cc @SuvarnaMeenakshi

sanmalho-git · 2021-11-11T00:14:05Z

My approach to fixing this is to

create an almost empty asic topology file for our multi-asic linecard with slot0.
In config_sonic_basedon_testbed.yml, when dealing with ‘voq’ switch_type, before running through the Jinja2 templates, change ‘slot0’ in the asic_topo_config to the ‘slot_num’ that is defined in the inventory.

I have prototyped with this solution, and works fine for both single and multi-asic linecards in a VoQ chassis.

Below is the asic topology for our multi-asic linecard Nokia_IXR7250e_36x400G card (in vars/topo_Nokia_IXR7250e_36x400G.yml) that I prototyped with:

slot0:
    ASIC0:
      topology:
        NEIGH_ASIC:
      configuration_properties:
        common:
          asic_type: FrontEnd 
      configuration:

    ASIC1:
      topology:
        NEIGH_ASIC:
      configuration_properties:
        common:
          asic_type: FrontEnd
      configuration:

Please let me know if you are OK with the approach

abdosi · 2021-11-12T00:25:33Z

My approach to fixing this is to

create an almost empty asic topology file for our multi-asic linecard with slot0.

In config_sonic_basedon_testbed.yml, when dealing with ‘voq’ switch_type, before running through the Jinja2 templates, change ‘slot0’ in the asic_topo_config to the ‘slot_num’ that is defined in the inventory.

I have prototyped with this solution, and works fine for both single and multi-asic linecards in a VoQ chassis.

Below is the asic topology for our multi-asic linecard Nokia_IXR7250e_36x400G card (in vars/topo_Nokia_IXR7250e_36x400G.yml) that I prototyped with:
slot0:
    ASIC0:
      topology:
        NEIGH_ASIC:
      configuration_properties:
        common:
          asic_type: FrontEnd 
      configuration:

    ASIC1:
      topology:
        NEIGH_ASIC:
      configuration_properties:
        common:
          asic_type: FrontEnd
      configuration:
Please let me know if you are OK with the approach

Thanks @sanmalho-git this looks fine to me . I assume this is for Problem#2. What about Problem#1 ?

sanmalho-git · 2021-11-12T00:36:24Z

For problem#1, there are some minor fixes in minigraph_cpg.j2.

Also, if I can get the command to generate minigraph of the packet-based chassis topology, that would help me test the solution out for packet based chassis as well.

abdosi · 2021-11-12T00:39:39Z

For problem#1, there are some minor fixes in minigraph_cpg.j2.

Also, if I can get the command to generate minigraph of the packet-based chassis topology, that would help me test the solution out for packet based chassis as well.

thanks @sanmalho-git Can you create PR for now ? I will take your change and verify. Not sure current public code will work to generate chassis-packet template. Will create seprate to make it work if not working.

PR# 4479 added support for minigraph generation for packet based chassis. However, this broke the generated minigraph for linecards in a VoQ chassis. There were two issues in the minigraph generated with PR sonic-net#4479: - In Cpg - Missing BGPRouterDeclaration section for remote asics - <remote_linecard>-ASIC<#> - For multi-asic linecard, missing BGPRouterDeclaraion section for my asics - ASIC<#> - In Dpg, we are missing the DeviceDataPlaneInfo for my asics in a multi-asic linecard - This is generated in template_dpg_asic, which is dependent on asic_topo_config. For voq_chassis, asic_topo_config is empty dictionary - as the iBGP connections depend on the what linecards are present in the chassis, and also what asics are on each linecard. To fix the above issues: - create an almost empty asic topology file for our multi-asic linecard with slot0. - In config_sonic_basedon_testbed.yml, when dealing with voq switch_type, before running through the Jinja2 templates, change slot0 in the asic_topo_config to the slot_num that is defined in the inventory. Below is the asic topology for our multi-asic linecard Nokia_IXR7250e_36x400G card (in vars/topo_Nokia_IXR7250e_36x400G.yml) that I prototyped with: slot0: ASIC0: topology: NEIGH_ASIC: configuration_properties: common: asic_type: FrontEnd configuration: ASIC1: topology: NEIGH_ASIC: configuration_properties: common: asic_type: FrontEnd configuration:

sanmalho-git · 2021-11-15T15:07:07Z

@abdosi @SuvarnaMeenakshi - PR #4699 has been raised to address the issues with minigraph generation for linecards in a VoQ chasiss. Please review and also add the 'chassis' label to the PR.

PR sonic-net#4479 introduced "slot" to hwsku topology definition. After this PR is merged, parsing topology of Nexus 3164 failed because its topology definition file in sonic-mgmt-int repo is not updated accordingly. This change added "slot to topo_Nexus-3164.yml to conform with the new "slot" requirement. Signed-off-by: Xin Wang <xiwang5@microsoft.com>

Add slot to topology definition of Nexus 3164 PR sonic-net#4479 introduced "slot" to hwsku topology definition. After this PR is merged, parsing topology of Nexus 3164 failed because its topology definition file in sonic-mgmt-int repo is not updated accordingly. This change added "slot to topo_Nexus-3164.yml to conform with the new "slot" requirement. Signed-off-by: Xin Wang <xiwang5@microsoft.com>

abdosi added 13 commits February 5, 2021 17:00

Added test case to verify ebtables rules.

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Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>

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abdosi requested a review from a team as a code owner October 13, 2021 14:26

abdosi force-pushed the chassis-pkt branch from 7dae835 to 7d32c91 Compare October 13, 2021 14:33

abdosi changed the title ~~Chassis pkt~~ Support for minigraph generation for packet based chassis. Oct 13, 2021

abdosi requested review from arlakshm and SuvarnaMeenakshi October 13, 2021 14:41

sanmalho-git reviewed Oct 13, 2021

View reviewed changes

sanmalho-git reviewed Oct 15, 2021

View reviewed changes

abdosi added 2 commits October 15, 2021 14:50

Some fixes.

690cc62

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>

Fixes

b3edd81

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>

arlakshm approved these changes Oct 19, 2021

View reviewed changes

abdosi merged commit d7fbdcf into sonic-net:master Oct 19, 2021

abdosi deleted the chassis-pkt branch October 19, 2021 01:43

SuvarnaMeenakshi mentioned this pull request Oct 27, 2021

Add Bandwidth in DeviceInterfaceLink #4572

Merged

4 tasks

sanmalho-git mentioned this pull request Nov 15, 2021

Fixes to minigraph generation for linecards in a VoQ Chassis #4699

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4 tasks

abdosi added the chassis label Apr 21, 2022

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Support for minigraph generation for packet based chassis. #4479

Support for minigraph generation for packet based chassis. #4479

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Support for minigraph generation for packet based chassis. #4479

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