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[P4-Symbolic]:Initial inport of Ir Table entries and test Code. #287

Merged
merged 4 commits into from
Jul 5, 2024
Merged

[P4-Symbolic]:Initial inport of Ir Table entries and test Code. #287

merged 4 commits into from
Jul 5, 2024

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VSuryaprasad-HCL
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Build Result:

sonic-buildimage/src/sonic-p4rt/sonic-pins/p4_symbolic$ ./key.sh .
Keyword check Passed.

sonic/src/sonic-p4rt/sonic-pins$ bazel build $BAZEL_BUILD_OPTS ...
bazel-out/k8-fastbuild/bin/external/com_github_google_glog/_virtual_includes/glog/glog/logging.h:211:53: note: in definition of macro 'GOOGLE_PREDICT_TRUE'
  211 | #define GOOGLE_PREDICT_TRUE(x) (__builtin_expect(!!(x), 1))
      |                                                     ^
bazel-out/k8-fastbuild/bin/external/com_github_google_glog/_virtual_includes/glog/glog/logging.h:852:1: note: in expansion of macro 'DEFINE_CHECK_OP_IMPL'
  852 | DEFINE_CHECK_OP_IMPL(Check_EQ, ==)  // Compilation error with CHECK_EQ(NULL, x)?
      | ^~~~~~~~~~~~~~~~~~~~
INFO: Elapsed time: 4091.686s, Critical Path: 103.48s
INFO: 6584 processes: 1645 internal, 4939 linux-sandbox.
INFO: Build completed successfully, 6584 total actions

sonic/src/sonic-p4rt/sonic-pins$ bazel test $BAZEL_BUILD_OPTS --cache_test_results=no ...
INFO: Analyzed 311 targets (0 packages loaded, 270 targets configured).
INFO: Found 195 targets and 116 test targets...
INFO: Elapsed time: 114.841s, Critical Path: 20.59s
INFO: 121 processes: 128 linux-sandbox, 17 local.
INFO: Build completed successfully, 121 total actions
//gutil:collections_test                                                 PASSED in 0.7s
//sai_p4/instantiations/google/tests:p4_constraints_integration_test     PASSED in 0.9s
//sai_p4/tools:p4info_tools_test                                         PASSED in 0.7s
//sai_p4/instantiations/google/test_tools:table_entry_generator_test     PASSED in 14.1s
  Stats over 5 runs: max = 14.1s, min = 1.1s, avg = 4.8s, dev = 4.8s

Executed 116 out of 116 tests: 116 tests pass.
INFO: Build completed successfully, 121 total actions

@divyagayathri-hcl
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divyagayathri-hcl commented Jul 4, 2024 •
edited
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@bhagatgit, Could you please review.
Thanks.

@bhagatgit bhagatgit merged commit 0907a44 into sonic-net:main Jul 5, 2024
2 checks passed
rkavitha-hcl pushed a commit to rkavitha-hcl/sonic-pins that referenced this pull request Jul 8, 2024
@VSuryaprasad-HCL @bhagatgit @rkavitha-hcl
[p4_symbolic]:Initial inport of Ir Table entries and test Code. (soni…
4695f72 
…c-net#287)

Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>
bhagatgit added a commit that referenced this pull request Jul 8, 2024
@rkavitha-hcl @VSuryaprasad-HCL
@bhagatgit @jonathan-dilorenzo @smolkaj
[SAIP4] Model tunnel termination (aka decap). (#283)
abd606e 
* [p4_symbolic]:Initial inport of Ir Table entries and test Code. (#287)

Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>

* [SAIP4] Add ACL ingress security table to Middleblock and update match fields for ToR.
Reserve 2 entries in the VRF bank.

* Limit ToR ACL pre-ingress table to 127 entries.

* [SAI P4] Model tunnel termination (aka decap).

---------

Co-authored-by: VSuryaprasad-hcl <159443973+VSuryaprasad-HCL@users.noreply.github.com>
Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>
Co-authored-by: jonathan-dilorenzo <dilo@google.com>
Co-authored-by: smolkaj <smolkaj@google.com>
bhagatgit added a commit that referenced this pull request Jul 9, 2024
@rkavitha-hcl @VSuryaprasad-HCL
@bhagatgit @jonathan-dilorenzo @smolkaj @rhalstea
[SAIP4] Pull logic for configuring BMv2 for SAI P4 into reusable help…
f983b38 
…er library allow ECN matching in the pre-ingress table. [arriba-lite] Add absl flag parsing/unparsing for ClosStage. Use packetIn matchers for BMv2 tests and re-use test packetlib::Packet across different tests. (#284)

* [p4_symbolic]:Initial inport of Ir Table entries and test Code. (#287)

Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>

* [SAIP4] Add ACL ingress security table to Middleblock and update match fields for ToR.
Reserve 2 entries in the VRF bank.

* Limit ToR ACL pre-ingress table to 127 entries.

* [SAI P4] Model tunnel termination (aka decap).

* [SAIP4] Add ACL ingress security table to Middleblock and update match fields for ToR.
Reserve 2 entries in the VRF bank.

* [SAI P4] Model tunnel termination (aka decap).

* [SAIP4] Pull logic for configuring BMv2 for SAI P4 into reusable helper library
allow ECN matching in the pre-ingress table.
[arriba-lite] Add absl flag parsing/unparsing for ClosStage.
Use packetIn matchers for BMv2 tests and re-use test packetlib::Packet across different tests.

---------

Co-authored-by: VSuryaprasad-hcl <159443973+VSuryaprasad-HCL@users.noreply.github.com>
Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>
Co-authored-by: jonathan-dilorenzo <dilo@google.com>
Co-authored-by: smolkaj <smolkaj@google.com>
Co-authored-by: rhalstea <rhalstea@google.com>
divyagayathri-hcl pushed a commit to divyagayathri-hcl/sonic-pins that referenced this pull request Jul 12, 2024
@VSuryaprasad-HCL @bhagatgit @divyagayathri-hcl
[p4_symbolic]:Initial inport of Ir Table entries and test Code. (soni…
823d8de 
…c-net#287)

Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>
divyagayathri-hcl pushed a commit to divyagayathri-hcl/sonic-pins that referenced this pull request Jul 12, 2024
@rkavitha-hcl @VSuryaprasad-HCL
@bhagatgit @jonathan-dilorenzo @smolkaj @divyagayathri-hcl
[SAIP4] Model tunnel termination (aka decap). (sonic-net#283)
e26a3d4 
* [p4_symbolic]:Initial inport of Ir Table entries and test Code. (sonic-net#287)

Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>

* [SAIP4] Add ACL ingress security table to Middleblock and update match fields for ToR.
Reserve 2 entries in the VRF bank.

* Limit ToR ACL pre-ingress table to 127 entries.

* [SAI P4] Model tunnel termination (aka decap).

---------

Co-authored-by: VSuryaprasad-hcl <159443973+VSuryaprasad-HCL@users.noreply.github.com>
Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>
Co-authored-by: jonathan-dilorenzo <dilo@google.com>
Co-authored-by: smolkaj <smolkaj@google.com>
divyagayathri-hcl pushed a commit to divyagayathri-hcl/sonic-pins that referenced this pull request Jul 12, 2024
@rkavitha-hcl @VSuryaprasad-HCL
@bhagatgit @jonathan-dilorenzo @smolkaj @rhalstea @divyagayathri-hcl
[SAIP4] Pull logic for configuring BMv2 for SAI P4 into reusable help…
141bb8e 
…er library allow ECN matching in the pre-ingress table. [arriba-lite] Add absl flag parsing/unparsing for ClosStage. Use packetIn matchers for BMv2 tests and re-use test packetlib::Packet across different tests. (sonic-net#284)

* [p4_symbolic]:Initial inport of Ir Table entries and test Code. (sonic-net#287)

Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>

* [SAIP4] Add ACL ingress security table to Middleblock and update match fields for ToR.
Reserve 2 entries in the VRF bank.

* Limit ToR ACL pre-ingress table to 127 entries.

* [SAI P4] Model tunnel termination (aka decap).

* [SAIP4] Add ACL ingress security table to Middleblock and update match fields for ToR.
Reserve 2 entries in the VRF bank.

* [SAI P4] Model tunnel termination (aka decap).

* [SAIP4] Pull logic for configuring BMv2 for SAI P4 into reusable helper library
allow ECN matching in the pre-ingress table.
[arriba-lite] Add absl flag parsing/unparsing for ClosStage.
Use packetIn matchers for BMv2 tests and re-use test packetlib::Packet across different tests.

---------

Co-authored-by: VSuryaprasad-hcl <159443973+VSuryaprasad-HCL@users.noreply.github.com>
Co-authored-by: bhagatgit <115375369+bhagatgit@users.noreply.github.com>
Co-authored-by: jonathan-dilorenzo <dilo@google.com>
Co-authored-by: smolkaj <smolkaj@google.com>
Co-authored-by: rhalstea <rhalstea@google.com>
@VSuryaprasad-HCL VSuryaprasad-HCL changed the title [p4_symbolic]:Initial inport of Ir Table entries and test Code. [P4-Symbolic]:Initial inport of Ir Table entries and test Code. Aug 26, 2024
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@bhagatgit bhagatgit bhagatgit approved these changes

@divyagayathri-hcl divyagayathri-hcl divyagayathri-hcl approved these changes

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@VSuryaprasad-HCL @divyagayathri-hcl @bhagatgit