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[sonic-pcie] Add unit testcases for pcie_common.py #293

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ArunSaravananBalachandran
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Description

Add unit testcases for pcie_common.py
Code coverage improved to 86%.

Motivation and Context

To improve code coverage for pcie_common.py

How Has This Been Tested?

abalac@f38b3ed3cc02:/sonic/src/sonic-platform-common/tests$ pytest-3 pcie_common_test.py
================================================================================ test session starts =================================================================================
platform linux -- Python 3.7.3, pytest-3.10.1, py-1.7.0, pluggy-0.8.0 -- /usr/bin/python3
cachedir: .pytest_cache
rootdir: /sonic/src/sonic-platform-common, inifile: pytest.ini
plugins: pyfakefs-4.5.6, cov-2.6.0
collected 4 items

pcie_common_test.py::TestPcieCommon::test_get_pcie_devices PASSED                                                                                                              [ 25%]
pcie_common_test.py::TestPcieCommon::test_get_pcie_check PASSED                                                                                                                [ 50%]
pcie_common_test.py::TestPcieCommon::test_get_pcie_aer_stats PASSED                                                                                                            [ 75%]
pcie_common_test.py::TestPcieCommon::test_dump_conf_yaml PASSED                                                                                                                [100%]

Additional Information (Optional)

@ArunSaravananBalachandran
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/easycla

@sujinmkang sujinmkang self-requested a review August 31, 2022 22:42
@sujinmkang
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pcie_common.py | 96 | 15 | 111 | 146 | 86.4%

@sujinmkang sujinmkang merged commit 9400720 into sonic-net:master Aug 31, 2022
dprital added a commit to dprital/sonic-buildimage that referenced this pull request Sep 4, 2022
Update sonic-platform-common submodule pointer to include the following:
* [CMIS] 'get_transceiver_info' should return 'None' when CMIS cable EEPROM is not ready  ([sonic-net#305](sonic-net/sonic-platform-common#305))
* uplift code coverage 80% ([sonic-net#307](sonic-net/sonic-platform-common#307))
* [sonic-pcie] Add UT for pcie_common.py ([sonic-net#293](sonic-net/sonic-platform-common#293))
* [CMIS] Catch Exception to avoid CMIS code crash ([sonic-net#299](sonic-net/sonic-platform-common#299))
* [Credo][Ycable] fix incorrect uart statistics ([sonic-net#296](sonic-net/sonic-platform-common#296))
* Add PSU input voltage and input current ([sonic-net#295](sonic-net/sonic-platform-common#295))

Signed-off-by: dprital <drorp@nvidia.com>
oleksandrivantsiv pushed a commit to oleksandrivantsiv/sonic-platform-common that referenced this pull request Oct 25, 2024
* Fix xcvrd to support 400G ZR/DR optics

* Fix xcvrd to support 400G ZR/DR optics

* Revert changes in DomInfoUpdateTask::on_port_config_change

* Fix xcvrd test after modifying on_port_config_change

* Call get_datapath_init_duration to get the init expiration time.

* Address comments

1. Clean up comments.
2. Revert port breakout fix and corresponding test change.
3. Check deinit duration for deinit case
4. Check datapath init pending

* 1. Revert changes in on_port_update_event
2. check DpInitPending on module which supports CMIS 5.0
3. Specify sec in return value

* Add code coverage

* Add log for DpInit/DpDeinit duration
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2 participants