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Chloe 280SE hardware reference
The Chloe 280SE is an 8/16-bit microcomputer, implemented as an FPGA core for the ZX Uno rev 4.1 hardware. It has a 60Hz interrupt and produces a VGA signal. It uses a CPU that is instruction compatible with the Z80. Its video hardware supports the display modes of the Timex T/S2068 and the ULAplus palette system.
Manufacturer: Chloe Corporation
Codename: Chloe GS
I/N: TS3280
Type: microcomputer
Generation: 16-bit
Media: FAT32 formatted SD card.
Operating System: UnoDOS 3
CPU: R80 @ 33MHz
Memory: 512 KB (32 KB used as VRAM)
40 KB ROM (SE Basic IV / UnoDOS 3)
Display: VGA / DVI-I
Graphics: up to 640x200 pixels, up to 256 colors, raster interrupt
Sound: dual YM2149F, buzzer, dual 8-bit DAC
Input: PS/2 keyboard, mouse, 2x DE9 joystick.
Predecessor: ZX Spectrum SE
The central processing unit (CPU) core is a minimal-cycle Z80-instruction compatible design with an intended clock speed of 33MHz. Ideally it should not have any wait states for opcode fetches, data or I/O. It is named after the R800 CPU in the MSX Turbo-R but does not feature that chip's additional instructions. It should use a full 16-bit ALU. The data bus remains 8-bit, as in the MC68008. It should be possible to slow it down to 1MHz to run at roughly the equivalent of a 3.5MHz Z80.
The R80 CPU has a 16-bit address space. 24-bit memory addressing is handled by the DMA/blitter. Legacy RAM paging is also supported. RAM not contended. The 280SE combines the RAM paging systems of the Timex TS2068 with the ZX Spectrum 128 for a total of 256K of HOME RAM, 32K of which is available to the video chip. The Timex-compatihble Horizontal MMU sees the RAM as three banks of memory; HOME, DOCK, and EX banks. DOCK and EX banks are overlaid on this bank, but paging over the screen area does not change the RAM used by the video chip. This means it is possible to set up a screen and page it out. Timex memory is mapped in 8K pages from either the DOCK or the EX bank, but these banks are mutually exclusive - you cannot map in a page from both simultaneously. Bit 7 of port #FF determines which bank to use (0=DOCK, 1=EX). Port #F4 determines which pages are mapped in with each bit referencing the relevant page (0-7 or 0'-7'). When memory is being mapped, interrupts should be disabled and the stack should be in an area which is not going to change.
The Chloe 280SE uses the 23K version of SE Basic IV. ROM 0 contains the bootstrap code and ROM 1 is paged in after boot. Other ROMs can be loaded in RAM if required for emulation. The ROM/CS line will replace whatever is connected to the low 16K address space (HOME, DOCK or EX) with external RAM/ROM (required for divMMC to work with emulation ROMs).
SE Basic IV is a 23K program stored in a 32K ROM. ROM 0 sets up the character sets and copies the final part of the program to the memory area $4000 to $5BFF. After initial setup, no further ROM paging takes place. By default, SE Basic IV maps in DOCK over pages 2 and 5 during initialization. This provides a contiguous block of 32K RAM in the area $4000 to $BFFF with 128K available in eight pages in the top 16K of addressable RAM. Up to two of these pages may be used by the video chip still leaving an effective 128K of RAM available to the user.
Reading the horizontal MMU ports returns the last byte sent to them (even for port #FF). The HOME bank is paged in the same way as the Spectrum 128, using port #7FFD. Reading the port returns the last value written to the selected register.
D0-2: RAM bank (0-7) to map into memory at 0xc000.
D3: Select video area to be used by ULA; Bank 5 or Bank 7.
D4: Select ROM; 0 - Boot or 1 - BASIC.
D5-7: Not used.
HOME RAM banks 5 and 7 are used for the display file. The EX and DOCK banks are paged by the horizontal MMU.
HOME
$ffff +---------+---------++---------++--------+--------+--------+--------+---------+--------+---------+
| Ex 7 | Dock 7 || Bank 0 || Bank 1 | Bank 2 | Bank 3 | Bank 4 | Bank 5 | Bank 6 | Bank 7 |
| | || || |(also at| | |Screen 0'| |Screen 1'|
$e000 +---------+---------+| || | 0x8000)| | +-- -- -- + +-- -- -- +
| Ex 6 | Dock 6 || || | | | | | | |
| | || || | | | |Screen 0 | |Screen 1 |
$c000 +---------+---------++---------++--------+--------+--------+--------+---------+--------+---------+
| Ex 5 | Dock 5 || Bank 2 | Any one of these pages may be switched in.
| | || |
$a000 +---------+---------+| |
| Ex 4 | Dock 4 || |
| | || |
$8000 +---------+---------++---------+
| Ex 3 | Dock 3 || Bank 5 |
| | ||Screen 0'|
$6000 +---------+---------++-- -- -- +
| Ex 2 | Dock 2 || |
| | ||Screen 0 |
$4000 +---------+---------++---------++--------+
| Ex 1 | Dock 1 || ROM 0 || ROM 1 | Either ROM may be
| | || || | mapped in.
$2000 +---------+---------+| || |
| Ex 0 | Dock 0 || || |
| | || Boot || BASIC |
$0000 +---------+---------++---------++--------+
The EX and DOCK banks
are mutually exclusive.
Pages from these banks
may be switched in over
the HOME bank.
In normal operation, the memory map is as follows:
HOME VRAM
$FFFF +---------+ +---------+---------+
| Bank 0 | | Bank 5h | Bank 7h |
| | |Screen 0'|Screen 1'|
$E000 + | +---------+---------+
| | | Bank 5l | Bank 7l |
| | |Screen 0 |Screen 1 |
$C000 +---------+ +---------+---------+
| Dock 5 |
| | .
$A000 +---------+ .
| Dock 4 | .
| | |
$8000 +---------+ +- User program
| Dock 3 | |
| | |
$6000 +---------+ |
| Dock 2 + $5C00 -+
| | |
$4000 +---------+ |
| ROM 1 | |
| | +- BASIC monitor
$2000 + | |
| | |
| BASIC | |
$0000 +---------+ -------+
The video display processor (VDP) core generates a progressive 720×240 pixel picture that is line-doubled to 720×480 pixels. The programmable area can contain up to 128,000 pixels. The core has a fixed palette of 256 colors (G3R3B2). Using 32K of shared VRAM, the core supports various combinations of resolution, color depth, encoding, line data format and frame buffer size. Only certain combinations are supported. Any screen line can use any display mode, although there are some practical limitations on this. Through the use of palette switching, it is possible to display all 256 colors on screen in any screen mode.
- 160 x 200 (wide pixels)
- 256 x 192
- 320 x 200
- 512 x 192 (tall pixels)
- 640 x 200 (tall pixels)
- 2 color
- 16 color
- 64 color
- 256 color
- 2 bits per pixel
- 4 bits per pixel
- 8 bits per pixel
- attributes (byte)
- attributes (cell)
- arbitrary
- high-byte offset
- linear
- 7 K
- 12 K
- 32 K
The VDP uses the ULAplus palette (and I/O ports). It supports the Timex video modes in either video page (5 or 7), with or without ULAplus. It also provides four new modes. Video modes are selected via port #FF:
-
000– 256×192 (cell attributes) Spectrum [1] -
001– 256×192 (offset cell attributes) Offset Spectrum [1][2] -
010– 256×192 (byte attributes) Timex 8x1 [1] -
011– 160×200 × 8bpp (256 colors) chunky [3][5] -
100– 320/640×200 × 4/2bpp (16 colors/line from 256) low/med res [4][5] -
101– 320×200 × 4bpp (15 colors/line from 256) filled [4][5][6] -
110– 512×192 × 1bpp (2 colors from 256) Timex mono [1] -
111– 320/640 × 200 (byte attributes) low/med res [4][5][7]
- With or without ULAplus.
- Offset from start of VRAM page by $2000.
- Standard screen size on C64, Amstrad CPC.
- Standard screen size on Atari ST, Amiga.
- Following the bitmap data there are 200 entries that specify the offset to the start of each line of data and 200 entries that specify which of 256 palettes to use for each line. This requires a total of 4096 palette registers.
- In filled mode, zero is replaced with the previous value written to the screen. This limits the number of colors per line to 15 from each palette.
- Attibute byte is offset by 160 bytes from the bitmap byte. Attributes have foreground/background as per VIC II hi-res mode. Low bits of the attribute byte are background. High bits are foreground.
D3-5: Sets the BRIGHT screen colour in hi-res mode.
000 - Black on white. 100 - Green on magenta.
001 - Blue on yellow. 101 - Cyan on red.
010 - Red on cyan. 110 - Yellow on blue.
011 - Magenta on green. 111 - White on black.
D6: If set disables the generation of the timer interrupt.*
D7: Selects which bank the horizontal MMU should use. 0=DOCK, 1=EX.
* may want to revist this, and consider the raster interrupt
Modes 011, 100, 101 and 111 use both banks of VRAM. The first 16,364 bytes are stored in page 5 at offset zero. The second 16,384 bytes are stored in page 7 at offset zero. These modes always use the ULAplus palette.
Some of the video modes enable the programmer to specify the arrangement of the screen in VRAM and wheteher
VRAM offset
0000-7CFF: avaialble for bitmap
7D00-7E8F: d0-14 = address offset of each of the 200 scanlines.
d15 = 320 pixels (not set) or 640 pixels (set).
7F00-7FC7: which 16 color palette to use for a given scanline.
ULAplus is controlled by two ports. Port #BF3B is the register port (write only). The byte output is interpreted as follows:
- Bits 0-5: Select the register sub-group
- Bits 6-7: Select the register group.
Two groups are available:
- 00 - Palette Group. When this group is selected, the sub-group determines the entry in the palette table (0-63).
- 01 - Table Group. When this group is selected, the sub group determines which of the palette tables (0-63) to write to. This gives a total of 4096 palette registers.
Port #FF3B is the data port (read/write). When the Palette group is selected, the byte written describes the color. When the Table group is selected, the byte output will be interpreted as follows for Spectrum/Timex video modes only: bit 0: ULAplus™ palette on (1) or off (0) Reading from port #FF3B returns the last data byte written to the currently selected register. This can be used to read back the current palette or determine if palette mode is active for Spectrum/Timex video modes. Implementations that support the Timex video modes use port #FF as the primary means to set the video mode, as per the Timex machines. It is left to the individual implementations to determine if reading the port returns the previous write or the floating bus. Note: Modes 2 to 63 are reserved for future use. Groups 10 and 11 are reserved for future use.
For a device using the GRB color space, the palette entry is interpreted as follows:
- bits 0-1: Blue Intensity
- bits 2-4: Red Intensity
- bits 5-7: Green Intensity
This color space uses a sub-set of 9-bit GRB. The missing lowest blue bit is set to the OR of the other two blue bits (Bb becomes 000 for 00, and Bb1 for anything else). This gives access to a fixed half the potential 512 color palette. This reduces the jump in intensity in the lower range in the earlier version of the specification. It also means the standard palette can now be represented by the ULAplus™ palette. Although in theory 64 colors can be displayed at once, in practice this is typically not possible except when displaying color bars, because the four CLUTs are mutually exclusive; it is not possible to mix colors from two CLUTs in the same cell. However, with software palette cycling it is possible to display all 256 colors on screen at once.
The 64 color mode look-up table is organized as four palettes of 16 colors. Bits 7 and 6 of each attribute byte, normally used for FLASH and BRIGHT, are used as an index value (0-3) to select one of the four color palettes. Each color palette has 16 entries: eight for INK, and eight for PAPER. Bits 0-2 (INK) and 3-5 (PAPER) of the attribute byte are used as indexes to retrieve color data from the selected palette. With the standard Spectrum display, the BORDER color is the same as the PAPER color in the first CLUT. For example BORDER 0 would set the border to the same color as PAPER 0 (with the BRIGHT and FLASH bits not set). The complete index can be calculated as:
- ink color = (FLASH * 2 + BRIGHT) * 16 + INK
- paper color = (FLASH * 2 + BRIGHT) * 16 + PAPER + 8
When scaling 3-bits of color data to more bits for emulators that operate in high color mode, simply concatenate the bits repeatedly and then truncate to as many bits as needed. For example, for 8-bits the following conversion should be used:
76543210-
hmlhmlhmwhere h is the high bit, m is the middle bit, and l is the low bit of the original 3-bit value. With the Timex hi-res display, the BORDER color is the same as the PAPER color in the second CLUT. Bits 3-5 of port #FF set the INK, PAPER, and BORDER values to the following ULAplus palette registers:
BITS INK PAPER BORDER
000 24 31 31
001 25 30 30
010 26 29 29
011 27 28 28
100 28 27 27
101 29 26 26
110 30 25 25
111 31 24 24
The floating point unit (FPU) core provides 40-bit floating point arithmetic operations:
- Addition
- Subtraction
- Multiplication
- Division
;fsub x36
;fmul x37
;fdiv x13
;fadd x34
; example ADD operation
; STKEND points to end of calculator stack
ld hl, (stkend); // next free entry in calculator stack
push hl; // save it for write back
dec hl; // point to last byte of value on stack
ld bc, $103B; // FPU port range = ($013B to $0A3B)
otdr; // write two 40-bit numbers to the FPU registers
ld a, fadd; // op-code
out (c), a; // BC = $003B (op-code port)
pop hl; // HL = stkend
ld b, $5; // BC = $053B (first register) - result is order-reversed
inir; // write result to calculator stack
ld (stkend), hl; // udpate stackend.
; need to double check what order OTDR and INIR do the various operations in.
; this has the advantage of a single op code to write or read the registers.
; the down side is it uses a lot of port addresses, but the up-side is that you can
; directly access each byte of either of the registers
; FPU should take R1 and R2 and put the result in reverse order in R1.
; I've used the ZXI ports because #3B is safe. Unfortunately it clashes with SpectraNet
; but there's no way around it as OTDR and INIR stop on B = 0.
The general logic unit (GLU) core provides integration for all the components that are not covered by other coprocessors, such as memory paging.
Port #FE deals with basic I/O. As mentioned before addresses are fully decoded, so whereas on a normal Spectrum every even I/O address will address the ULA, the 280SE will only respond to the correct port. The port is decoded as follows:
D0-2: Border
D3: MIC
D4: EAR/beeper
IN: Reads keys (bit 0 to bit 4 inclusive)
#fefe SHIFT, Z, X, C, V #effe 0, 9, 8, 7, 6
#fdfe A, S, D, F, G #dffe P, O, I, U, Y
#fbfe Q, W, E, R, T #bffe ENTER, L, K, J, H
#f7fe 1, 2, 3, 4, 5 #7ffe SPACE, SYM SHFT, M, N, B
The Lambda (Linear Address Memory Blitter and Direct Access) chip performs 24-bit direct memory access (DMA) and bit blit (blitter) functions.
; blitter
; parameter format (little endian)
; source: 24-bit address
; mask: 24-bit address
; dest: 24-bit address
; screen width: 16-bit (160 to 640)
; rectangle width: 16-bit (1 to 640)
; rectangle depth: 16-bit (1 to 200)
; operand: 8-bit
; operands:
; $00 - copy source to dest
; $01 - copy source (and mask) to dest
; $02 - fill dest with zero
; $03 - swap source/dest
; $04 - copy mirror of source/mask to dest
; $05 - copy flip of source/mask to dest
; $06 - copy mirror/flip of source/mask to dest
; PARAMS points to 16 bytes of data (see parameter format)
ld hl, params; // blitter data
ld bc, $0F7F; // let's use the ZX printer port
otir; // write 15 bytes of data to the relevant ports ($0f7f to $017f)
ld a, (hl); // get the operand
out (c),a; // do the blitter operation (#007F)
Paged memory appears in the following order:
3C000 - 3FFFF : HOME 7 (upper VRAM)
38000 - 3BFFF : HOME 5 (lower VRAM)
34000 - 37FFF : HOME 3
30000 - 33FFF : HOME 1
2C000 - 3FFFF : HOME 0 (paged at C000 in 16-bit address space)
28000 - 3BFFF : HOME 2 (page at 8000 in 16-bit address space)
24000 - 37FFF : HOME 4
20000 - 33FFF : HOME 6
10000 - 1FFFF : EX (eight 8K pages)
00000 - 0FFFF : DOCK (eight 8K pages)
The following operations are supported:
AND
NOT
OR
XOR
Up to two sources and a destination are specified.
Optionally, a window is defined (for screen updates).
Data can be written backwards or forwards as with Z80 block copy operations. Source data can be mirrored (read in one direction and written back in the opposite direction to flip an image horizonatally).
Using the DMA halts the CPU.
The programmable sound generator (PSG) core provides:
- Dual YM2149F chips (six channel waveform sound)
- Dual 8-bit DACs
- 1-bit buzzer
- Stereo mixer
The 280SE has two YM2149F chips in the TurboSound-AY configuration connected to the 128 and Timex ports (dual mapping).
These ports match the AY chip used in the ZX Spectrum 128:
- OUT (0xfffd) - Select a register 0-14.
- IN (0xfffd) - Read the value of the selected register.
- OUT (0xbffd) - Write to the selected register.
These ports match the AY chip used in the Timex TS2068:
- OUT (0xf5) - Select a register 0-14
- IN (0xf5) - Read the value of the selected register
- OUT (0xf6) - Write to the selected register
The sound mix is controlled by port #F7 (sets the mix for the currently selected PSG). There are two channels for the beeper. When one channel is active the beeper is at the same volume level as a single PSG channel at full volume. When both are active and have the same pan it is then double the volume of a single PSG channel. This approximates the relative loudness of the beeper on 128K machines.
D6-7: channel A
D4-5: channel B
D3-2: channel C
D1-0: channel D (beeper)
Panning is limited to switching a channel on or off for a given speaker. The bits are decoded as follows:
00 = mute
10 = left
01 = right
11 = both
The default port value on reset is zero (all channels off).
The joystick is configurable. By default it uses the Kempston standard on port #1F.
K-mouse is supported on the standard port via PS/2.
#..FF - Alicia / Cola (Timex control) register
#..FE - Cola (GPIO) registers
#..FD - Cola(MMU) registers
#..FC - Lambda registers
#..FA - Arturo (FPU) registers
#..F8 - Laura (PSG) mixer
#..F6 - Laura (PSG) data port
#..F5 - Laura (PSG) register select
#..F4 - Cola (Timex MMU) register
#..EB - MMC SPI
#..E7 - MMC device
#..E3 - MMC RAM
#..3B - ZXI registers
$7C000: HOME 7 \_ 32K frame
$78000: HOME 5 / buffer
$74000: HOME 3
$70000: HOME 1
$6C000: HOME 0
$68000: HOME 2
$64000: HOME 4
$60000: HOME 6
$5C000: DMA 7
$58000: DMA 6
$54000: DMA 5
$50000: DMA 4
$4C000: DMA 3
$48000: DMA 2
$44000: DMA 1
$40000: DMA 0
$3C000: DOCK 6 / 7
$38000: DOCK 4 / 5
$34000: DOCK 2 / 3
$30000: DOCK 0 / 1
$2C000: EX 6 / 7
$28000: EX 4 / 5
$24000: EX 2 / 3
$20000: EX 0 / 1
$1C000: MMCRAM 9 / A
$18000: MMCRAM 7 / 8
$14000: MMCRAM 5 / 6
$10000: MMCRAM 3 / 4
$0C000: MMCRAM 1 / 2
$08000: MMCROM / MMCRAM 0
$04000: ROM1
$00000: ROM0
Physical RAM map after booting
---------------
$C000 HOME 0
$8000 EX 4 / 5
$4000 EX 2 / 3
$0000 ROM 1
This documentation is copyright © 2012-2022 Source Solutions, Inc. Portions copyright © 2014-2019 Rob Hagemans.
Licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.