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Siarhei Siamashka edited this page Mar 26, 2016 · 30 revisions

Memory performance benchmark results

MIPS
Hardware CPU type and clock frequency Best read speed Best write speed Best direct copy speed Best 2-pass copy speed Random reads latency in 64MiB block
Asus RT N16 (BCM4718) MIPS74K
480 MHz 		- 797 MB/s 356 MB/s 255 MB/s 554.9 ns
ARM
Hardware CPU type and clock frequency Best read speed Best write speed Best direct copy speed Best 2-pass copy speed Random reads latency in 64MiB block
Raspberry Pi (BCM2708), one 1920x1080-32@60Hz monitor ARM11
700 MHz 		- 1194 MB/s 333 MB/s 254 MB/s 432.0 ns
Raspberry Pi (BCM2708) ARM11
700 MHz 		- 1476 MB/s 388 MB/s 291 MB/s 379.5 ns
Nokia N900 (OMAP3430) Cortex-A8 600 MHz 591 MB/s 531 MB/s 406 MB/s 283 MB/s 342.9 ns
Allwinner-A13 Cortex-A8 1000 MHz 856 MB/s 1006 MB 500 MB/s 415 MB/s 341.2 ns
IGEPv2 board (DM3730), 1280x1024-32@57Hz monitor Cortex-A8 1000 MHz 924 MB/s 938 MB/s (backwards) 395 MB/s 392 MB/s 259.2 ns
IGEPv2 board (DM3730) Cortex-A8 1000 MHz 1125 MB/s 1547 MB/s 611 MB/s 582 MB/s 250.5 ns
Mele A2000 (Allwinner A10), two 1920x1080-32@60Hz monitors Cortex-A8 1000 MHz 814 MB/s 519 MB/s 352 MB/s 305 MB/s 254.8 ns
Mele A2000 (Allwinner A10), one 1920x1080-32@60Hz monitor Cortex-A8 1000 MHz 1224 MB/s 1040 MB/s (backwards) 625 MB/s (backwards) 521 MB/s 221.1 ns
Mele A2000 (Allwinner A10) Cortex-A8 1000 MHz 1326 MB/s 1467 MB/s 921 MB/s 639 MB/s 221.8 ns
ODROID-X board (Exynos4412) Cortex-A9 1400 MHz 1900 MB/s 2606 MB/s 1146 MB/s 932 MB/s 163.1 ns
Samsung Chromebook XE303C12 (Exynos5250) Cortex-A15 1700 MHz 4865 MB/s 6069 MB/s 3467 MB/s 2668 MB/s 159.3 ns
x86
Hardware CPU type and clock frequency Best read speed Best write speed Best direct copy speed Best 2-pass copy speed Random reads latency in 64MiB block
Samsung N220 (Intel Atom N450) Intel Atom 1667 MHz - 3031 MB/s 1183 MB/s (without MOVNTDQ) 1202 MB/s 169.0 ns
ThinkPad T61 (Intel Core2 T7300) Intel Core2 2000 MHz - 3646 MB/s 1366 MB/s (without MOVNTDQ) 1312 MB/s 104.9 ns
  • 2-pass copy means that we are using a small temporary buffer to first fetch data into it, and only then write it to the destination (source -> L1 cache, L1 cache -> destination)
Add a custom footer

Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.

tinymembench v0.4.9 (simple benchmark for memory thr

==========================================================================
== Memory bandwidth tests                                               ==
==                                                                      ==
== Note 1: 1MB = 1000000 bytes                                          ==
== Note 2: Results for 'copy' tests show how many bytes can be          ==
==         copied per second (adding together read and writen           ==
==         bytes would have provided twice higher numbers)              ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
==         to first fetch data into it, and only then write it to the   ==
==         destination (source -> L1 cache, L1 cache -> destination)    ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in    ==
==         brackets                                                     ==
==========================================================================

 C copy backwards                                     :   2949.7 MB/s (3.8%)
 C copy backwards (32 byte blocks)                    :   3011.8 MB/s
 C copy backwards (64 byte blocks)                    :   3029.2 MB/s
 C copy                                               :   3642.2 MB/s (4.1%)
 C copy prefetched (32 bytes step)                    :   3824.4 MB/s (0.3%)
 C copy prefetched (64 bytes step)                    :   3825.3 MB/s (0.4%)
 C 2-pass copy                                        :   2726.2 MB/s
 C 2-pass copy prefetched (32 bytes step)             :   2902.6 MB/s (2.5%)
 C 2-pass copy prefetched (64 bytes step)             :   2928.3 MB/s (0.3%)
 C fill                                               :   8541.0 MB/s (0.2%)
 C fill (shuffle within 16 byte blocks)               :   8518.5 MB/s (2.1%)
 C fill (shuffle within 32 byte blocks)               :   8537.1 MB/s (0.1%)
 C fill (shuffle within 64 byte blocks)               :   8528.7 MB/s (0.2%)
 ---
 standard memcpy                                      :   3558.8 MB/s
 standard memset                                      :   8520.2 MB/s
 ---
 NEON LDP/STP copy                                    :   3633.9 MB/s (4.2%)
 NEON LDP/STP copy pldl2strm (32 bytes step)          :   1451.0 MB/s (0.3%)
 NEON LDP/STP copy pldl2strm (64 bytes step)          :   1450.9 MB/s (0.5%)
 NEON LDP/STP copy pldl1keep (32 bytes step)          :   3882.5 MB/s (3.9%)
 NEON LDP/STP copy pldl1keep (64 bytes step)          :   3884.0 MB/s (0.4%)
 NEON LD1/ST1 copy                                    :   3630.8 MB/s (0.3%)
 NEON STP fill                                        :   8537.8 MB/s
 NEON STNP fill                                       :   8544.9 MB/s (1.7%)
 ARM LDP/STP copy                                     :   3635.8 MB/s (0.3%)
 ARM STP fill                                         :   8544.8 MB/s (0.1%)
 ARM STNP fill                                        :   8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests.                                              ==
==                                                                      ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled.       ==
== Writes to such framebuffers are quite fast, but reads are much       ==
== slower and very sensitive to the alignment and the selection of      ==
== CPU instructions which are used for accessing memory.                ==
==                                                                      ==
== Many x86 systems allocate the framebuffer in the GPU memory,         ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover,    ==
== PCI-E is asymmetric and handles reads a lot worse than writes.       ==
==                                                                      ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer    ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall    ==
== performance improvement. For example, the xf86-video-fbturbo DDX     ==
== uses this trick.                                                     ==
==========================================================================

 NEON LDP/STP copy (from framebuffer)                 :    766.0 MB/s
 NEON LDP/STP 2-pass copy (from framebuffer)          :    688.8 MB/s
 NEON LD1/ST1 copy (from framebuffer)                 :    770.6 MB/s (0.1%)
 NEON LD1/ST1 2-pass copy (from framebuffer)          :    681.3 MB/s (0.3%)
 ARM LDP/STP copy (from framebuffer)                  :    766.1 MB/s
 ARM LDP/STP 2-pass copy (from framebuffer)           :    689.1 MB/s


==========================================================================
== Memory latency test                                                  ==
==                                                                      ==
== Average time is measured for random memory accesses in the buffers   ==
== of different sizes. The larger is the buffer, the more significant   ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM      ==
== accesses. For extremely large buffer sizes we are expecting to see   ==
== page table walk with several requests to SDRAM for almost every      ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest).                                         ==
==                                                                      ==
== Note 1: All the numbers are representing extra time, which needs to  ==
==         be added to L1 cache latency. The cycle timings for L1 cache ==
==         latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
==         two independent memory accesses at a time. In the case if    ==
==         the memory subsystem can't handle multiple outstanding       ==
==         requests, dual random read has the same timings as two       ==
==         single reads performed one after another.                    ==
==========================================================================

block size : single random read / dual random read, [MADV_NOHUGEPAGE]
      1024 :    0.0 ns          /     0.1 ns 
      2048 :    0.0 ns          /     0.1 ns 
      4096 :    0.0 ns          /     0.1 ns 
      8192 :    0.0 ns          /     0.1 ns 
     16384 :    0.1 ns          /     0.1 ns 
     32768 :    1.7 ns          /     2.9 ns 
     65536 :    6.4 ns          /     9.5 ns 
    131072 :    9.6 ns          /    12.3 ns 
    262144 :   13.7 ns          /    17.0 ns 
    524288 :   15.8 ns          /    19.7 ns 
   1048576 :   17.3 ns          /    22.1 ns 
   2097152 :   42.1 ns          /    64.2 ns 
   4194304 :   98.5 ns          /   138.1 ns 
   8388608 :  143.9 ns          /   186.3 ns 
  16777216 :  167.2 ns          /   211.2 ns 
  33554432 :  180.1 ns          /   227.1 ns 
  67108864 :  200.0 ns          /   260.2 ns 
block size : single random read / dual random read, [MADV_HUGEPAGE]
      1024 :    0.0 ns          /     0.0 ns 
      2048 :    0.0 ns          /     0.0 ns 
      4096 :    0.0 ns          /     0.0 ns 
      8192 :    0.0 ns          /     0.0 ns 
     16384 :    0.0 ns          /     0.0 ns 
     32768 :    0.0 ns          /     0.0 ns 
     65536 :    6.4 ns          /     9.4 ns 
    131072 :    9.5 ns          /    12.2 ns 
    262144 :   11.2 ns          /    13.1 ns 
    524288 :   12.1 ns          /    13.5 ns 
   1048576 :   12.8 ns          /    13.6 ns 
   2097152 :   27.0 ns          /    33.0 ns 
   4194304 :   90.6 ns          /   127.8 ns 
   8388608 :  123.9 ns          /   153.8 ns 
  16777216 :  139.5 ns          /   161.2 ns 
  33554432 :  147.2 ns          /   163.6 ns 
  67108864 :  154.0 ns          /   167.6 ns
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