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Tronsmart Vega S95 (Amlogic S905)
Cosmin Gorgovan edited this page Oct 13, 2016
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2 revisions
processor : 0 BogoMIPS : 2.00 Features : fp asimd crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 1 BogoMIPS : 2.00 Features : fp asimd crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 2 BogoMIPS : 2.00 Features : fp asimd crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 3 BogoMIPS : 2.00 Features : fp asimd crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 Hardware : Amlogic Revision : 020b
cpufrequtils 008: cpufreq-info (C) Dominik Brodowski 2004-2009
Report errors and bugs to cpufreq@vger.kernel.org, please.
analyzing CPU 0:
driver: meson_cpufreq
CPUs which run at the same hardware frequency: 0 1 2 3
CPUs which need to have their frequency coordinated by software: 0 1 2 3
maximum transition latency: 200 us.
hardware limits: 100.0 MHz - 1.54 GHz
available frequency steps: 100.0 MHz, 250 MHz, 500 MHz, 1000 MHz, 1.30 GHz, 1.54 GHz
available cpufreq governors: hotplug, interactive, conservative, ondemand, userspace, powersave, performance
current policy: frequency should be within 100.0 MHz and 1.54 GHz.
The governor "performance" may decide which speed to use
within this range.
current CPU frequency is 1.54 GHz (asserted by call to hardware).
cpufreq stats: 100.0 MHz:14.88%, 250 MHz:8.11%, 500 MHz:15.17%, 1000 MHz:0.94%, 1.30 GHz:0.25%, 1.54 GHz:60.64% (1882)
[...]
$ echo 1 | sudo tee /sys/devices/platform/meson-fb/graphics/fb0/blank
AArch64:
$ CFLAGS=-mcpu=cortex-a53 make
$ ./tinymembench
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1669.3 MB/s (1.8%)
C copy backwards (32 byte blocks) : 1724.0 MB/s (1.0%)
C copy backwards (64 byte blocks) : 1749.5 MB/s (2.3%)
C copy : 1750.8 MB/s (1.8%)
C copy prefetched (32 bytes step) : 1242.5 MB/s
C copy prefetched (64 bytes step) : 1342.8 MB/s
C 2-pass copy : 1510.8 MB/s
C 2-pass copy prefetched (32 bytes step) : 988.1 MB/s
C 2-pass copy prefetched (64 bytes step) : 556.0 MB/s (0.4%)
C fill : 3742.5 MB/s
C fill (shuffle within 16 byte blocks) : 3742.5 MB/s
C fill (shuffle within 32 byte blocks) : 3742.8 MB/s
C fill (shuffle within 64 byte blocks) : 3742.4 MB/s
---
standard memcpy : 1770.9 MB/s
standard memset : 3743.8 MB/s
---
NEON LDP/STP copy : 1761.2 MB/s (0.3%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 1102.2 MB/s (0.5%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1371.1 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 2177.3 MB/s
NEON LDP/STP copy pldl1keep (64 bytes step) : 2179.0 MB/s
NEON LD1/ST1 copy : 1764.5 MB/s (0.2%)
NEON STP fill : 3744.1 MB/s
NEON STNP fill : 2721.3 MB/s (0.2%)
ARM LDP/STP copy : 1741.6 MB/s
ARM STP fill : 3744.1 MB/s
ARM STNP fill : 2721.9 MB/s (0.3%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 222.6 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 212.7 MB/s
NEON LD1/ST1 copy (from framebuffer) : 58.9 MB/s
NEON LD1/ST1 2-pass copy (from framebuffer) : 58.2 MB/s
ARM LDP/STP copy (from framebuffer) : 114.4 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 111.7 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.4 ns / 7.4 ns
131072 : 6.8 ns / 10.2 ns
262144 : 8.0 ns / 11.3 ns
524288 : 10.4 ns / 15.1 ns
1048576 : 73.8 ns / 112.7 ns
2097152 : 105.6 ns / 144.6 ns
4194304 : 127.7 ns / 160.4 ns
8388608 : 139.4 ns / 166.7 ns
16777216 : 146.8 ns / 172.2 ns
33554432 : 151.3 ns / 176.8 ns
67108864 : 154.0 ns / 176.5 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.4 ns / 7.5 ns
131072 : 6.8 ns / 10.4 ns
262144 : 8.0 ns / 11.3 ns
524288 : 10.4 ns / 15.1 ns
1048576 : 73.8 ns / 112.7 ns
2097152 : 105.5 ns / 144.5 ns
4194304 : 121.9 ns / 155.8 ns
8388608 : 130.2 ns / 160.2 ns
16777216 : 134.2 ns / 162.1 ns
33554432 : 136.2 ns / 157.0 ns
67108864 : 137.3 ns / 158.2 ns
AArch32:
$ CC=arm-linux-gnueabihf-gcc CFLAGS="-mcpu=cortex-a53 -mfpu=neon-fp-armv8" make
$ ./tinymembench
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1670.2 MB/s (1.4%)
C copy backwards (32 byte blocks) : 1667.3 MB/s (0.6%)
C copy backwards (64 byte blocks) : 1697.3 MB/s (0.8%)
C copy : 1718.3 MB/s (2.2%)
C copy prefetched (32 bytes step) : 1862.7 MB/s
C copy prefetched (64 bytes step) : 1862.5 MB/s
C 2-pass copy : 1449.6 MB/s
C 2-pass copy prefetched (32 bytes step) : 1533.7 MB/s
C 2-pass copy prefetched (64 bytes step) : 1564.3 MB/s
C fill : 3742.1 MB/s
C fill (shuffle within 16 byte blocks) : 3738.8 MB/s
C fill (shuffle within 32 byte blocks) : 3741.8 MB/s
C fill (shuffle within 64 byte blocks) : 3741.6 MB/s
---
standard memcpy : 1759.2 MB/s (0.6%)
standard memset : 3717.3 MB/s
---
NEON read : 1926.7 MB/s (0.3%)
NEON read prefetched (32 bytes step) : 3636.8 MB/s
NEON read prefetched (64 bytes step) : 3636.9 MB/s
NEON read 2 data streams : 1834.1 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 3632.8 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 3640.0 MB/s
NEON copy : 1765.7 MB/s (0.2%)
NEON copy prefetched (32 bytes step) : 1921.9 MB/s (0.4%)
NEON copy prefetched (64 bytes step) : 1943.7 MB/s (0.2%)
NEON unrolled copy : 1755.1 MB/s
NEON unrolled copy prefetched (32 bytes step) : 2311.7 MB/s
NEON unrolled copy prefetched (64 bytes step) : 2327.6 MB/s
NEON copy backwards : 1696.4 MB/s (0.2%)
NEON copy backwards prefetched (32 bytes step) : 1821.0 MB/s (0.5%)
NEON copy backwards prefetched (64 bytes step) : 1808.5 MB/s (0.4%)
NEON 2-pass copy : 1553.1 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 1682.0 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 1681.1 MB/s
NEON unrolled 2-pass copy : 1412.5 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1674.2 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1801.3 MB/s
NEON fill : 3742.9 MB/s
NEON fill backwards : 3742.7 MB/s
VFP copy : 1757.5 MB/s (0.2%)
VFP 2-pass copy : 1441.4 MB/s
ARM fill (STRD) : 3717.5 MB/s
ARM fill (STM with 8 registers) : 3740.2 MB/s
ARM fill (STM with 4 registers) : 3735.9 MB/s
ARM copy prefetched (incr pld) : 1862.0 MB/s
ARM copy prefetched (wrap pld) : 1850.9 MB/s
ARM 2-pass copy prefetched (incr pld) : 1488.9 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1485.8 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON read (from framebuffer) : 58.6 MB/s
NEON copy (from framebuffer) : 58.4 MB/s
NEON 2-pass copy (from framebuffer) : 57.9 MB/s
NEON unrolled copy (from framebuffer) : 58.5 MB/s
NEON 2-pass unrolled copy (from framebuffer) : 57.8 MB/s
VFP copy (from framebuffer) : 414.5 MB/s
VFP 2-pass copy (from framebuffer) : 384.9 MB/s
ARM copy (from framebuffer) : 212.0 MB/s (0.1%)
ARM 2-pass copy (from framebuffer) : 208.2 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.4 ns / 7.4 ns
131072 : 6.8 ns / 10.2 ns
262144 : 8.0 ns / 11.4 ns
524288 : 10.4 ns / 15.1 ns
1048576 : 73.8 ns / 112.7 ns
2097152 : 105.5 ns / 144.5 ns
4194304 : 127.6 ns / 162.6 ns
8388608 : 139.5 ns / 171.2 ns
16777216 : 146.8 ns / 176.5 ns
33554432 : 151.3 ns / 180.3 ns
67108864 : 153.9 ns / 182.8 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.4 ns / 7.4 ns
131072 : 6.8 ns / 10.2 ns
262144 : 8.0 ns / 11.3 ns
524288 : 10.4 ns / 15.2 ns
1048576 : 73.9 ns / 112.7 ns
2097152 : 105.5 ns / 144.5 ns
4194304 : 121.9 ns / 155.8 ns
8388608 : 130.2 ns / 160.2 ns
16777216 : 134.2 ns / 156.8 ns
33554432 : 136.2 ns / 158.8 ns
67108864 : 137.3 ns / 160.9 ns
Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.
tinymembench v0.4.9 (simple benchmark for memory thr
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2949.7 MB/s (3.8%)
C copy backwards (32 byte blocks) : 3011.8 MB/s
C copy backwards (64 byte blocks) : 3029.2 MB/s
C copy : 3642.2 MB/s (4.1%)
C copy prefetched (32 bytes step) : 3824.4 MB/s (0.3%)
C copy prefetched (64 bytes step) : 3825.3 MB/s (0.4%)
C 2-pass copy : 2726.2 MB/s
C 2-pass copy prefetched (32 bytes step) : 2902.6 MB/s (2.5%)
C 2-pass copy prefetched (64 bytes step) : 2928.3 MB/s (0.3%)
C fill : 8541.0 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 8518.5 MB/s (2.1%)
C fill (shuffle within 32 byte blocks) : 8537.1 MB/s (0.1%)
C fill (shuffle within 64 byte blocks) : 8528.7 MB/s (0.2%)
---
standard memcpy : 3558.8 MB/s
standard memset : 8520.2 MB/s
---
NEON LDP/STP copy : 3633.9 MB/s (4.2%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 1451.0 MB/s (0.3%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1450.9 MB/s (0.5%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 3882.5 MB/s (3.9%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 3884.0 MB/s (0.4%)
NEON LD1/ST1 copy : 3630.8 MB/s (0.3%)
NEON STP fill : 8537.8 MB/s
NEON STNP fill : 8544.9 MB/s (1.7%)
ARM LDP/STP copy : 3635.8 MB/s (0.3%)
ARM STP fill : 8544.8 MB/s (0.1%)
ARM STNP fill : 8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 766.0 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 688.8 MB/s
NEON LD1/ST1 copy (from framebuffer) : 770.6 MB/s (0.1%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 681.3 MB/s (0.3%)
ARM LDP/STP copy (from framebuffer) : 766.1 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 689.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.1 ns / 0.1 ns
32768 : 1.7 ns / 2.9 ns
65536 : 6.4 ns / 9.5 ns
131072 : 9.6 ns / 12.3 ns
262144 : 13.7 ns / 17.0 ns
524288 : 15.8 ns / 19.7 ns
1048576 : 17.3 ns / 22.1 ns
2097152 : 42.1 ns / 64.2 ns
4194304 : 98.5 ns / 138.1 ns
8388608 : 143.9 ns / 186.3 ns
16777216 : 167.2 ns / 211.2 ns
33554432 : 180.1 ns / 227.1 ns
67108864 : 200.0 ns / 260.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.4 ns / 9.4 ns
131072 : 9.5 ns / 12.2 ns
262144 : 11.2 ns / 13.1 ns
524288 : 12.1 ns / 13.5 ns
1048576 : 12.8 ns / 13.6 ns
2097152 : 27.0 ns / 33.0 ns
4194304 : 90.6 ns / 127.8 ns
8388608 : 123.9 ns / 153.8 ns
16777216 : 139.5 ns / 161.2 ns
33554432 : 147.2 ns / 163.6 ns
67108864 : 154.0 ns / 167.6 ns