Description
NOTE: I am reposting my forum post here for greater visibility.
The BeagleV beta boards have the StarFive 7100 SoC which was from a limited multi-project wafer run. We only have enough chips to produce 300 BeagleV beta boards. StarFive should be releasing a public datasheet next week for the 7100. The 7100 has 2x StarFive U74 cores.
StarFive will be putting in a full production order an updated design called the 7110. This will have 4x SiFive U74 cores as well as Imagination GPU and PCIe controller.
This brings me to design issues in the 7100:
- L2 cache controller has a bug where it incorrectly raises the L2 DirFail interrupt. The only work around for this is to mask the L2 cache interrupt on the PLIC.
- All the peripherals in the 7100 are on a non-coherent bus. StarFive refers to this as the sysbus port. This requires the drivers to flush L2 cache in many instances where it is not necessary on other SoC’s. This design choice reduces the performance of the 7100.
StarFive tells me that they have resolved the L2 cache controller DirFail interrupt bug in the 7110. And more importantly they have improved the SoC architecture. High performance peripherals like the Gigabit Ethernet and USB3 controller will be connected to a cache-coherent bus (StarFive refers to it as the front port).
My understanding so far is that it may be difficult to upstream the 7100 support given that the peripherals are not coherent. I would very much like to get input from you and others in the beta as to what the correct way to implement the drivers might be.
I also need to work with StarFive to create some diagrams of the SoC architecture that shows exactly how the different IP blocks are interconnected and whether or not those connections are coherent.
Thank you,
Drew Fustini
BeagleBoard.org Foundation