Skip to content

watchdog: Add StarFive SI5 watchdog driver #47

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
andyhu-stf merged 1 commit into from
Jan 13, 2022
Merged

watchdog: Add StarFive SI5 watchdog driver #47

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 14 additions & 0 deletions arch/riscv/boot/dts/starfive/jh7100.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -133,6 +133,20 @@
reg-names = "control";
};

wdog: wdog@12480000 {
compatible = "starfive,si5-wdt";
reg = <0x0 0x12480000 0x0 0x10000>;
interrupt-parent = <&plic>;
interrupts = <80>;
interrupt-names = "wdog";
clocks = <&clkgen JH7100_CLK_WDT_CORE>,
<&clkgen JH7100_CLK_WDTIMER_APB>;
clock-names = "core_clk", "apb_clk";
clock-frequency = <50000000>;
timeout-sec = <15>;
status = "okay";
};

plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
Expand Down
9 changes: 8 additions & 1 deletion drivers/clk/starfive/clk-starfive-jh7100.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -456,6 +456,8 @@ static int __init starfive_clkgen_init(struct clk_starfive_jh7100_priv *priv)
#define CLK_GMAC 16
#define CLK_HF 17
#define CLK_RTC 18
#define CLK_WDT_APB 19
#define CLK_WDT_CORE 20

struct clk_hw **hws = priv->clk_hws.hws;
extern bool clk_ignore_unused;
Expand Down Expand Up @@ -483,7 +485,9 @@ static int __init starfive_clkgen_init(struct clk_starfive_jh7100_priv *priv)
[CLK_SPI] = { "spi", .mult = 2, .div = 1 },
[CLK_GMAC] = { "gmac", .mult = 1, .div = 1 },
[CLK_HF] = { "hf", .mult = 1, .div = 1 },
[CLK_RTC] = { "rtc", .mult = 1, .div = 4 }
[CLK_RTC] = { "rtc", .mult = 1, .div = 4 },
[CLK_WDT_APB] = { "wdt_apb", .mult = 5, .div = 1},
[CLK_WDT_CORE] = { "wdt_core", .mult = 2, .div = 1},
};
unsigned int i;

Expand Down Expand Up @@ -516,6 +520,9 @@ static int __init starfive_clkgen_init(struct clk_starfive_jh7100_priv *priv)
hws[JH7100_CLK_SPI2_CORE] = tmp_clks[CLK_SPI].hw;
// hws[JH7100_CLK_SPI3_CORE] = tmp_clks[CLK_SPI].hw;

hws[JH7100_CLK_WDTIMER_APB] = tmp_clks[CLK_WDT_APB].hw;
hws[JH7100_CLK_WDT_CORE] = tmp_clks[CLK_WDT_CORE].hw;

clk_ignore_unused = true;
}

Expand Down
9 changes: 9 additions & 0 deletions drivers/watchdog/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1998,6 +1998,15 @@ config UML_WATCHDOG
tristate "UML watchdog"
depends on UML || COMPILE_TEST

# RISCV Architecture

config STARFIVE_WATCHDOG
tristate "StarFive Watchdog support"
depends on RISCV
select WATCHDOG_CORE
help
Say Y here to support the starfive Si5 watchdog.

#
# ISA-based Watchdog Cards
#
Expand Down
3 changes: 3 additions & 0 deletions drivers/watchdog/Makefile
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -202,6 +202,9 @@ obj-$(CONFIG_WATCHDOG_SUN4V) += sun4v_wdt.o
# Xen
obj-$(CONFIG_XEN_WDT) += xen_wdt.o

# RISCV Architecture
obj-$(CONFIG_STARFIVE_WATCHDOG) += starfive-wdt.o

# Architecture Independent
obj-$(CONFIG_BD70528_WATCHDOG) += bd70528_wdt.o
obj-$(CONFIG_BD957XMUF_WATCHDOG) += bd9576_wdt.o
Expand Down
Loading