Add rtc module

Cargo.toml

@@ -21,6 +21,7 @@ cortex-m-rt = "0.6"
 embedded-hal = "0.2"
 nb = "0.1"
 stm32f3 = "0.11"
+rtcc = "0.2.0"
 
 [dependencies.bare-metal]
 version = "0.2"

src/lib.rs

@@ -127,6 +127,8 @@ pub mod pwm;
 #[cfg(feature = "device-selected")]
 pub mod rcc;
 #[cfg(feature = "device-selected")]
+pub mod rtc;
+#[cfg(feature = "device-selected")]
 pub mod serial;
 #[cfg(feature = "device-selected")]
 pub mod spi;

src/rcc.rs

@@ -20,13 +20,16 @@ impl RccExt for RCC {
             ahb: AHB { _0: () },
             apb1: APB1 { _0: () },
             apb2: APB2 { _0: () },
+            bdcr: BDCR { _0: () },
             cfgr: CFGR {
                 hse: None,
                 hclk: None,
                 pclk1: None,
                 pclk2: None,
                 sysclk: None,
             },
+            cr: CR { _0: () },
+            csr: CSR { _0: () },
         }
     }
 }
@@ -39,8 +42,14 @@ pub struct Rcc {
     pub apb1: APB1,
     /// Advanced Peripheral Bus 2 (APB2) registers
     pub apb2: APB2,
+    /// RCC Backup Domain
+    pub bdcr: BDCR,
     /// Clock configuration
     pub cfgr: CFGR,
+    /// RCC Clock Control register
+    pub cr: CR,
+    /// RCC Control/Status register
+    pub csr: CSR,
 }
 
 /// AMBA High-performance Bus (AHB) registers
@@ -157,7 +166,20 @@ mod usb_clocking {
     }
 }
 
+/// Backup Domain Control register (RCC_BDCR)
+pub struct BDCR {
+    _0: (),
+}
+
+impl BDCR {
+    pub(crate) fn bdcr(&mut self) -> &rcc::BDCR {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*RCC::ptr()).bdcr }
+    }
+}
+
 /// Clock configuration
+#[derive(Clone, Copy)]
 pub struct CFGR {
     hse: Option<u32>,
     hclk: Option<u32>,
@@ -580,6 +602,30 @@ impl CFGR {
     }
 }
 
+/// RCC Clock Control register (RCC_CR)
+pub struct CR {
+    _0: (),
+}
+
+impl CR {
+    pub(crate) fn cr(&mut self) -> &rcc::CR {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*RCC::ptr()).cr }
+    }
+}
+
+/// RCC Control/Status register
+pub struct CSR {
+    _0: (),
+}
+
+impl CSR {
+    pub(crate) fn csr(&mut self) -> &rcc::CSR {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*RCC::ptr()).csr }
+    }
+}
+
 /// Frozen clock frequencies
 ///
 /// The existence of this value indicates that the clock configuration can no longer be changed