fugit-rate & PERExt traits

CHANGELOG.md

@@ -17,6 +17,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Move `i2c` `embedded-hal` trait impls to `I2c` methods [#431]
 - Reexport pins in `gpio` module
 - Pwm channels now constants [#432]
+- Use fugit rate types instead of custom [#430]
 - Add channel events, make Event use bitflags (simplify interrupt handling) [#425]
 - reexport `digital::v2::PinState` again [#428]
 - Timer impls with time based on `fugit` moved to `fugit` module, added `Pwm` and `fugit-timer` impls [#423]
@@ -54,6 +55,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#440]: https://github.com/stm32-rs/stm32f4xx-hal/pull/440
 [#443]: https://github.com/stm32-rs/stm32f4xx-hal/pull/443
 [#441]: https://github.com/stm32-rs/stm32f4xx-hal/pull/441
+[#430]: https://github.com/stm32-rs/stm32f4xx-hal/pull/430
 
 ### Changed
 

Cargo.toml

@@ -41,7 +41,7 @@ cast = { default-features = false, version = "0.3.0" }
 void = { default-features = false, version = "1.0.2" }
 embedded-hal = { features = ["unproven"], version = "0.2.7" }
 display-interface = { version = "0.4.1", optional = true }
-fugit = "0.3.3"
+fugit = "0.3.5"
 fugit-timer = "0.1.3"
 rtic-monotonic = { version = "1.0", optional = true }
 bitflags = "1.3.2"

examples/adc_dma_rtic.rs

@@ -44,12 +44,12 @@ mod app {
         let rcc = device.RCC.constrain();
         let _clocks = rcc
             .cfgr
-            .use_hse(25.mhz())
+            .use_hse(25.MHz())
             .require_pll48clk()
-            .sysclk(84.mhz())
-            .hclk(84.mhz())
-            .pclk1(42.mhz())
-            .pclk2(84.mhz())
+            .sysclk(MONO_HZ.Hz())
+            .hclk(MONO_HZ.Hz())
+            .pclk1(42.MHz())
+            .pclk2(84.MHz())
             .freeze();
 
         let mut dcb = cx.core.DCB;

examples/analog-stopwatch-with-spi-ssd1306.rs

@@ -101,7 +101,7 @@ fn main() -> ! {
             polarity: Polarity::IdleLow,
             phase: Phase::CaptureOnFirstTransition,
         },
-        2000.khz(),
+        2000.kHz(),
         &clocks,
     );
 
@@ -209,10 +209,10 @@ fn main() -> ! {
 
 fn setup_clocks(rcc: Rcc) -> Clocks {
     rcc.cfgr
-        .hclk(180.mhz())
-        .sysclk(180.mhz())
-        .pclk1(45.mhz())
-        .pclk2(90.mhz())
+        .hclk(180.MHz())
+        .sysclk(180.MHz())
+        .pclk1(45.MHz())
+        .pclk2(90.MHz())
         .freeze()
 }
 

examples/blinky-timer-irq.rs

@@ -67,7 +67,7 @@ fn main() -> ! {
     let dp = Peripherals::take().unwrap();
 
     let rcc = dp.RCC.constrain();
-    let clocks = rcc.cfgr.sysclk(16.mhz()).pclk1(8.mhz()).freeze();
+    let clocks = rcc.cfgr.sysclk(16.MHz()).pclk1(8.MHz()).freeze();
 
     // Configure PA5 pin to blink LED
     let gpioa = dp.GPIOA.split();

examples/can-send.rs

@@ -10,7 +10,7 @@ use bxcan::filter::Mask32;
 use bxcan::{Frame, StandardId};
 use cortex_m_rt::entry;
 use nb::block;
-use stm32f4xx_hal::{can::Can, pac, prelude::*};
+use stm32f4xx_hal::{pac, prelude::*};
 
 #[entry]
 fn main() -> ! {
@@ -21,14 +21,16 @@ fn main() -> ! {
     // To meet CAN clock accuracy requirements an external crystal or ceramic
     // resonator must be used. The blue pill has a 8MHz external crystal.
     // Other boards might have a crystal with another frequency or none at all.
-    rcc.cfgr.use_hse(8.mhz()).freeze();
+    rcc.cfgr.use_hse(8.MHz()).freeze();
 
     let gpiob = dp.GPIOB.split();
     let mut can1 = {
         let rx = gpiob.pb8.into_alternate::<9>();
         let tx = gpiob.pb9.into_alternate();
 
-        let can = Can::new(dp.CAN1, (tx, rx));
+        // let can = Can::new(dp.CAN1, (tx, rx));
+        // or
+        let can = dp.CAN1.can((tx, rx));
 
         bxcan::Can::builder(can)
             // APB1 (PCLK1): 8MHz, Bit rate: 500kBit/s, Sample Point 87.5%
@@ -45,7 +47,7 @@ fn main() -> ! {
         let tx = gpiob.pb13.into_alternate();
         let rx = gpiob.pb12.into_alternate();
 
-        let can = Can::new(dp.CAN2, (tx, rx));
+        let can = dp.CAN2.can((tx, rx));
 
         let can2 = bxcan::Can::builder(can)
             // APB1 (PCLK1): 8MHz, Bit rate: 500kBit/s, Sample Point 87.5%

examples/delay-syst-blinky.rs

@@ -25,7 +25,7 @@ fn main() -> ! {
 
         // Set up the system clock. We want to run at 48MHz for this one.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(48.MHz()).freeze();
 
         // Create a delay abstraction based on SysTick
         let mut delay = hal::delay::Delay::new(cp.SYST, &clocks);

examples/delay-timer-blinky.rs

@@ -25,7 +25,7 @@ fn main() -> ! {
 
         // Set up the system clock. We want to run at 48MHz for this one.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.use_hse(25.mhz()).sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.use_hse(25.MHz()).sysclk(48.MHz()).freeze();
 
         // Create a delay abstraction based on general-pupose 32-bit timer TIM5
         let mut delay = dp.TIM5.delay_us(&clocks);

examples/dwt-blinky.rs

@@ -26,7 +26,7 @@ fn main() -> ! {
 
         // Set up the system clock. We want to run at 48MHz for this one.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(48.MHz()).freeze();
 
         // Create a delay abstraction based on DWT cycle counter
         let dwt = cp.DWT.constrain(cp.DCB, &clocks);

examples/f413disco_lcd_ferris.rs

@@ -706,7 +706,7 @@ fn main() -> ! {
 
         // Configure and lock the clocks at maximum warp
         let rcc = p.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(100.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(100.MHz()).freeze();
 
         // Define the pins we need for our 16bit parallel bus
         let lcd_pins = LcdPins {

examples/i2s-audio-out-dma.rs

@@ -93,7 +93,7 @@ fn main() -> ! {
 
     let rcc = dp.RCC.constrain();
     // The 86 MHz frequency can be divided to get a sample rate very close to 48 kHz.
-    let clocks = rcc.cfgr.use_hse(8.mhz()).i2s_clk(86.mhz()).freeze();
+    let clocks = rcc.cfgr.use_hse(8.MHz()).i2s_clk(86.MHz()).freeze();
 
     let gpioa = dp.GPIOA.split();
     let gpiob = dp.GPIOB.split();
@@ -108,7 +108,7 @@ fn main() -> ! {
             gpiob.pb6.into_alternate_open_drain(),
             gpiob.pb9.into_alternate_open_drain(),
         ),
-        100.khz(),
+        100.kHz(),
         &clocks,
     );
     // Shift the address to deal with different ways of representing I2C addresses
@@ -123,7 +123,9 @@ fn main() -> ! {
         gpioc.pc7.into_alternate(),
         gpioc.pc12.into_alternate(),
     );
-    let hal_i2s = I2s::new(dp.SPI3, i2s_pins, &clocks);
+    // let hal_i2s = I2s::new(dp.SPI3, i2s_pins, &clocks);
+    // or
+    let hal_i2s = dp.SPI3.i2s(i2s_pins, &clocks);
     let i2s_clock = hal_i2s.input_clock();
 
     // Audio timing configuration:
@@ -134,7 +136,7 @@ fn main() -> ! {
 
     let i2s = stm32_i2s_v12x::I2s::new(hal_i2s);
     let mut i2s = i2s.configure_master_transmit(MasterConfig::with_sample_rate(
-        i2s_clock.0,
+        i2s_clock.raw(),
         sample_rate,
         Data16Frame16,
         FrameFormat::PhilipsI2s,

examples/i2s-audio-out.rs

@@ -98,7 +98,7 @@ fn main() -> ! {
 
     let rcc = dp.RCC.constrain();
     // The 86 MHz frequency can be divided to get a sample rate very close to 48 kHz.
-    let clocks = rcc.cfgr.use_hse(8.mhz()).i2s_clk(86.mhz()).freeze();
+    let clocks = rcc.cfgr.use_hse(8.MHz()).i2s_clk(86.MHz()).freeze();
 
     let mut delay = Delay::new(cp.SYST, &clocks);
 
@@ -108,7 +108,7 @@ fn main() -> ! {
             gpiob.pb6.into_alternate_open_drain(),
             gpiob.pb9.into_alternate_open_drain(),
         ),
-        100.khz(),
+        100.kHz(),
         &clocks,
     );
     // Shift the address to deal with different ways of representing I2C addresses
@@ -134,7 +134,7 @@ fn main() -> ! {
 
     let i2s = stm32_i2s_v12x::I2s::new(hal_i2s);
     let mut i2s = i2s.configure_master_transmit(MasterConfig::with_sample_rate(
-        i2s_clock.0,
+        i2s_clock.raw(),
         sample_rate,
         Data16Frame16,
         FrameFormat::PhilipsI2s,

examples/ist7920_bidi_normal_spi.rs

@@ -7,7 +7,7 @@ use cortex_m_rt::entry;
 
 use stm32f4xx_hal as hal;
 
-use crate::hal::{pac, prelude::*, spi::Spi};
+use crate::hal::{pac, prelude::*};
 
 use hal::spi::{Mode, NoMiso, Phase, Polarity};
 
@@ -44,8 +44,9 @@ fn main() -> ! {
     };
 
     // Change spi transfer mode to Bidi for more efficient operations.
-    let spi =
-        Spi::new(dp.SPI1, (sck, miso, mosi), mode, 8_000_000.hz(), &clocks).to_bidi_transfer_mode();
+    // let spi = Spi::new(dp.SPI1, (sck, miso, mosi), mode, 8.MHz(), &clocks).to_bidi_transfer_mode();
+    // or
+    let spi = dp.SPI1.spi_bidi((sck, miso, mosi), mode, 8.MHz(), &clocks);
 
     let iface = SPIInterface::new(spi, dc, cs);
 

examples/pwm-input.rs

@@ -20,7 +20,7 @@ fn main() -> ! {
 
         let channels = (gpioa.pa8.into_alternate(), gpioa.pa9.into_alternate());
         // configure tim1 as a PWM output of known frequency.
-        let pwm = Timer::new(dp.TIM1, &clocks).pwm(channels, 501u32.hz());
+        let pwm = Timer::new(dp.TIM1, &clocks).pwm(channels, 501.Hz());
         let (mut ch1, _ch2) = pwm.split();
         let max_duty = ch1.get_max_duty();
         ch1.set_duty(max_duty / 2);
@@ -30,7 +30,7 @@ fn main() -> ! {
         let pwm_reader_ch1 = gpioc.pc6.into_alternate();
 
         // configure tim8 as a PWM input, using the best-guess frequency of the input signal.
-        let monitor = Timer::new(dp.TIM8, &clocks).pwm_input(500u32.hz(), pwm_reader_ch1);
+        let monitor = Timer::new(dp.TIM8, &clocks).pwm_input(500.Hz(), pwm_reader_ch1);
 
         // NOTE: this value may only be accurately observed at the CC2 interrupt.
         let _duty = monitor.get_duty_cycle();

examples/pwm-sinus.rs

@@ -15,7 +15,7 @@ fn main() -> ! {
     if let Some(dp) = pac::Peripherals::take() {
         // Set up the system clock.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.use_hse(25.mhz()).freeze();
+        let clocks = rcc.cfgr.use_hse(25.MHz()).freeze();
 
         let gpioa = dp.GPIOA.split();
         let channels = (gpioa.pa8.into_alternate(), gpioa.pa9.into_alternate());

examples/pwm.rs

@@ -18,9 +18,7 @@ fn main() -> ! {
         let gpioa = dp.GPIOA.split();
         let channels = (gpioa.pa8.into_alternate(), gpioa.pa9.into_alternate());
 
-        let pwm = Timer::new(dp.TIM1, &clocks)
-            .pwm(channels, 20u32.khz())
-            .split();
+        let pwm = Timer::new(dp.TIM1, &clocks).pwm(channels, 20.kHz()).split();
         let (mut ch1, _ch2) = pwm;
         let max_duty = ch1.get_max_duty();
         ch1.set_duty(max_duty / 2);

examples/rng-display.rs

@@ -61,8 +61,8 @@ fn main() -> ! {
         // from which RNG_CLK is derived, is about 48 MHz
         let clocks = rcc
             .cfgr
-            .use_hse(8.mhz()) //discovery board has 8 MHz crystal for HSE
-            .sysclk(128.mhz())
+            .use_hse(8.MHz()) //discovery board has 8 MHz crystal for HSE
+            .sysclk(128.MHz())
             .freeze();
 
         let mut delay_source = hal::delay::Delay::new(cp.SYST, &clocks);
@@ -73,7 +73,7 @@ fn main() -> ! {
         let gpiob = dp.GPIOB.split();
         let scl = gpiob.pb8.into_alternate().set_open_drain();
         let sda = gpiob.pb9.into_alternate().set_open_drain();
-        let i2c = I2c::new(dp.I2C1, (scl, sda), 400.khz(), &clocks);
+        let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &clocks);
 
         // Set up the display
         let interface = I2CDisplayInterface::new(i2c);

examples/rtic-tick.rs

@@ -26,7 +26,7 @@ mod app {
     #[init]
     fn init(ctx: init::Context) -> (Shared, Local, init::Monotonics) {
         let rcc = ctx.device.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(48.MHz()).freeze();
 
         let gpioc = ctx.device.GPIOC.split();
         let led = gpioc.pc13.into_push_pull_output();

examples/sd.rs

@@ -19,12 +19,12 @@ fn main() -> ! {
     let rcc = device.RCC.constrain();
     let clocks = rcc
         .cfgr
-        .use_hse(12.mhz())
+        .use_hse(12.MHz())
         .require_pll48clk()
-        .sysclk(168.mhz())
-        .hclk(168.mhz())
-        .pclk1(42.mhz())
-        .pclk2(84.mhz())
+        .sysclk(168.MHz())
+        .hclk(168.MHz())
+        .pclk1(42.MHz())
+        .pclk2(84.MHz())
         .freeze();
 
     assert!(clocks.is_pll48clk_valid());

examples/serial-9bit.rs

@@ -34,7 +34,7 @@ use panic_halt as _;
 use cortex_m_rt::entry;
 use stm32f4xx_hal as hal;
 
-use crate::hal::{block, pac, prelude::*, serial::config::Config, serial::Serial};
+use crate::hal::{block, pac, prelude::*, serial::config::Config};
 
 use core::ops::Range;
 
@@ -53,7 +53,7 @@ fn main() -> ! {
 
     let rcc = dp.RCC.constrain();
 
-    let clocks = rcc.cfgr.use_hse(8.mhz()).freeze();
+    let clocks = rcc.cfgr.use_hse(8.MHz()).freeze();
 
     let mut delay = hal::delay::Delay::new(cp.SYST, &clocks);
 
@@ -62,15 +62,16 @@ fn main() -> ! {
     let rx_pin = gpioa.pa3.into_alternate();
 
     // configure serial
-    let serial = Serial::new(
-        dp.USART2,
-        (tx_pin, rx_pin),
-        Config::default().baudrate(9600.bps()).wordlength_9(),
-        &clocks,
-    )
-    .unwrap()
-    // Make this Serial object use u16s instead of u8s
-    .with_u16_data();
+    let serial = dp
+        .USART2
+        .serial(
+            (tx_pin, rx_pin),
+            Config::default().baudrate(9600.bps()).wordlength_9(),
+            &clocks,
+        )
+        .unwrap()
+        // Make this Serial object use u16s instead of u8s
+        .with_u16_data();
 
     let (mut tx, mut rx) = serial.split();
 

examples/serial.rs

@@ -6,7 +6,7 @@ use panic_halt as _;
 use cortex_m_rt::entry;
 use stm32f4xx_hal as hal;
 
-use crate::hal::{pac, prelude::*, serial::Serial};
+use crate::hal::{pac, prelude::*};
 
 use core::fmt::Write; // for pretty formatting of the serial output
 
@@ -18,15 +18,17 @@ fn main() -> ! {
 
     let rcc = dp.RCC.constrain();
 
-    let clocks = rcc.cfgr.use_hse(25.mhz()).freeze();
+    let clocks = rcc.cfgr.use_hse(25.MHz()).freeze();
 
     let mut delay = dp.TIM1.delay_ms(&clocks);
 
     // define RX/TX pins
     let tx_pin = gpioa.pa9.into_alternate();
 
     // configure serial
-    let mut tx = Serial::tx(dp.USART1, tx_pin, 9600.bps(), &clocks).unwrap();
+    // let mut tx = Serial::tx(dp.USART1, tx_pin, 9600.bps(), &clocks).unwrap();
+    // or
+    let mut tx = dp.USART1.tx(tx_pin, 9600.bps(), &clocks).unwrap();
 
     let mut value: u8 = 0;