Skip to content

Commit

Permalink
repr-u32
Browse files Browse the repository at this point in the history
  • Loading branch information
burrbull committed Dec 6, 2023
1 parent 0ffa14c commit 26f646d
Show file tree
Hide file tree
Showing 5 changed files with 29 additions and 29 deletions.
14 changes: 7 additions & 7 deletions src/dma/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -301,7 +301,7 @@ impl Not for CurrentBuffer {

/// Structure to get or set common interrupts setup
#[enumflags2::bitflags]
#[repr(u8)]
#[repr(u32)]
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
pub enum DmaEvent {
DirectModeError = 1 << 1,
Expand Down Expand Up @@ -331,7 +331,7 @@ impl DmaEventExt for BitFlags<DmaEvent> {

/// Structure returned by Stream or Transfer flags() method.
#[enumflags2::bitflags]
#[repr(u8)]
#[repr(u32)]
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
pub enum DmaFlag {
FifoError = 1 << 0,
Expand Down Expand Up @@ -600,7 +600,7 @@ where

#[inline(always)]
fn events(&self) -> BitFlags<DmaEvent> {
BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits() as u8)
BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits())
}

#[inline(always)]
Expand Down Expand Up @@ -679,10 +679,10 @@ where
w.bits({
let mut bits = r.bits();
if let Some(d) = disable {
bits &= !(d.bits() as u32)
bits &= !d.bits()
}
if let Some(e) = enable {
bits |= e.bits() as u32;
bits |= e.bits();
}
bits
})
Expand All @@ -704,7 +704,7 @@ macro_rules! dma_stream {
#[inline(always)]
fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>) {
let dma = unsafe { &*I::ptr() };
dma.$ifcr.write(|w| unsafe { w.bits((flags.into().bits() as u32) << $isr_shift) });
dma.$ifcr.write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) });
}
}

Expand All @@ -717,7 +717,7 @@ macro_rules! dma_stream {
//NOTE(unsafe) Atomic read with no side effects
let dma = unsafe { &*I::ptr() };
BitFlags::from_bits_truncate(
((dma.$isr.read().bits() >> $isr_shift)) as u8
((dma.$isr.read().bits() >> $isr_shift))
)
}
}
Expand Down
6 changes: 3 additions & 3 deletions src/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ pub enum Error {
#[enumflags2::bitflags]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u16)]
#[repr(u32)]
pub enum Event {
/// IDLE interrupt enable
Idle = 1 << 4,
Expand All @@ -72,7 +72,7 @@ pub enum Event {
#[enumflags2::bitflags]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u16)]
#[repr(u32)]
pub enum Flag {
/// Parity error
ParityError = 1 << 0,
Expand Down Expand Up @@ -100,7 +100,7 @@ pub enum Flag {
#[enumflags2::bitflags]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u16)]
#[repr(u32)]
pub enum CFlag {
/// Read data register not empty
RxNotEmpty = 1 << 5,
Expand Down
5 changes: 2 additions & 3 deletions src/serial/uart_impls.rs
Original file line number Diff line number Diff line change
Expand Up @@ -282,12 +282,11 @@ macro_rules! uartCommon {
}

fn flags(&self) -> BitFlags<Flag> {
BitFlags::from_bits_truncate(self.sr.read().bits() as u16)
BitFlags::from_bits_truncate(self.sr.read().bits())
}

fn clear_flags(&self, flags: BitFlags<CFlag>) {
self.sr
.write(|w| unsafe { w.bits(0xffff & !(flags.bits() as u32)) });
self.sr.write(|w| unsafe { w.bits(0xffff & !flags.bits()) });
}

fn clear_idle_interrupt(&self) {
Expand Down
27 changes: 14 additions & 13 deletions src/spi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ use core::ops::{Deref, DerefMut};
use crate::dma::traits::{DMASet, PeriAddress};
use crate::dma::{MemoryToPeripheral, PeripheralToMemory};
use crate::gpio::{self, NoPin};
use crate::{pac, ClearFlags, ReadFlags};
use crate::{pac, ReadFlags};

/// Clock polarity
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
Expand Down Expand Up @@ -67,7 +67,7 @@ pub type NoMosi = NoPin;
#[enumflags2::bitflags]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u8)]
#[repr(u32)]
pub enum Event {
/// An error occurred.
///
Expand All @@ -90,7 +90,7 @@ pub enum Event {
#[enumflags2::bitflags]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u16)]
#[repr(u32)]
pub enum Flag {
/// Receive buffer not empty
RxNotEmpty = 1 << 0,
Expand All @@ -112,7 +112,7 @@ pub enum Flag {
#[enumflags2::bitflags]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u16)]
#[repr(u32)]
pub enum CFlag {
/// CRC error flag
CrcError = 1 << 4,
Expand Down Expand Up @@ -788,7 +788,7 @@ impl<SPI: Instance> Inner<SPI> {
Error::ModeFault.into()
} else if flags.contains(Flag::CrcError) {
// Clear the CRCERR bit
self.clear_flags(CFlag::CrcError);
self.spi.sr.modify(|_r, w| w.crcerr().clear_bit());
Error::Crc.into()
} else if flags.contains(Flag::TxEmpty) {
self.write_data_reg(byte);
Expand All @@ -802,10 +802,10 @@ impl<SPI: Instance> Inner<SPI> {
w.bits({
let mut bits = r.bits();
if let Some(d) = disable {
bits &= !(d.bits() as u32)
bits &= !d.bits();
}
if let Some(e) = enable {
bits |= e.bits() as u32;
bits |= e.bits();
}
bits
})
Expand All @@ -831,18 +831,19 @@ impl<SPI: Instance> crate::Listen for Inner<SPI> {

impl<SPI: Instance> crate::ClearFlags for Inner<SPI> {
type Flag = CFlag;
fn clear_flags(&mut self, event: impl Into<BitFlags<Self::Flag>>) {
// TODO: check
self.spi
.sr
.write(|w| unsafe { w.bits(0xffff & !(event.into().bits() as u32)) });
fn clear_flags(&mut self, flags: impl Into<BitFlags<Self::Flag>>) {
if flags.into().contains(CFlag::CrcError) {
self.spi
.sr
.write(|w| unsafe { w.bits(0xffff).crcerr().clear_bit() })
}
}
}

impl<SPI: Instance> crate::ReadFlags for Inner<SPI> {
type Flag = Flag;
fn flags(&self) -> BitFlags<Self::Flag> {
BitFlags::from_bits_truncate(self.spi.sr.read().bits() as u16)
BitFlags::from_bits_truncate(self.spi.sr.read().bits())
}
}

Expand Down
6 changes: 3 additions & 3 deletions src/timer.rs
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ pub enum SysEvent {

/// TIM interrupt events
#[enumflags2::bitflags]
#[repr(u8)]
#[repr(u32)]
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Event {
Expand All @@ -114,7 +114,7 @@ pub enum Event {

/// TIM status flags
#[enumflags2::bitflags]
#[repr(u16)]
#[repr(u32)]
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Flag {
Expand Down Expand Up @@ -450,7 +450,7 @@ macro_rules! hal {
}
#[inline(always)]
fn get_interrupt_flag(&self) -> BitFlags<Flag> {
BitFlags::from_bits_truncate(self.sr.read().bits() as u16)
BitFlags::from_bits_truncate(self.sr.read().bits())
}
#[inline(always)]
fn read_count(&self) -> Self::Width {
Expand Down

0 comments on commit 26f646d

Please sign in to comment.