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Merge branch 'master' into internal_pull_down
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@Windfisch
Windfisch authored Dec 13, 2021
2 parents 04aa233 + a817b40 commit 4af12ad
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3 changes: 3 additions & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Changed

- Finish SDIO data transmission before querying card status in `write_block` [#395]
- SDIO: Rewrite loop conditions to silence clippy
- Unify alternate pin constraints [#393]
- [breaking-change] Use `&Clocks` instead of `Clocks` [#387]
- Split and rename `GetBusFreq` -> `BusClock`, `BusTimerClock` [#386]
Expand All @@ -34,7 +35,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- [breaking-change] Bump `bxcan` to 0.6 [#371]
- [breaking-change] Change `Pin<Output<OpenDrain>>::internal_pull_up` signature from `(&mut self, _: bool) -> ()`
to `(self, _: bool) -> Self`. [#399]
- fix #362: ADC voltage conversion might be incorrect [#397]

[#367]: https://github.com/stm32-rs/stm32f4xx-hal/pull/397
[#367]: https://github.com/stm32-rs/stm32f4xx-hal/pull/367
[#371]: https://github.com/stm32-rs/stm32f4xx-hal/pull/371
[#383]: https://github.com/stm32-rs/stm32f4xx-hal/pull/383
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14 changes: 8 additions & 6 deletions src/adc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -605,7 +605,7 @@ pub struct Adc<ADC> {
adc_reg: ADC,
/// VDDA in millivolts calculated from the factory calibration and vrefint
calibrated_vdda: u32,
/// Maximum sample value possible for the configured resolution
/// Exclusive limit for the sample value possible for the configured resolution.
max_sample: u32,
}
impl<ADC> fmt::Debug for Adc<ADC> {
Expand Down Expand Up @@ -794,10 +794,10 @@ macro_rules! adc {
/// Sets the sampling resolution
pub fn set_resolution(&mut self, resolution: config::Resolution) {
self.max_sample = match resolution {
config::Resolution::Twelve => (1 << 12) - 1,
config::Resolution::Ten => (1 << 10) - 1,
config::Resolution::Eight => (1 << 8) - 1,
config::Resolution::Six => (1 << 6) -1,
config::Resolution::Twelve => (1 << 12),
config::Resolution::Ten => (1 << 10),
config::Resolution::Eight => (1 << 8),
config::Resolution::Six => (1 << 6),
};
self.config.resolution = resolution;
self.adc_reg.cr1.modify(|_, w| w.res().bits(resolution.into()));
Expand Down Expand Up @@ -954,7 +954,9 @@ macro_rules! adc {
self.adc_reg.dr.read().data().bits()
}

/// Converts a sample value to millivolts using calibrated VDDA and configured resolution
/// Converts a sample value to millivolts using calibrated VDDA and configured resolution.
/// Due to the ADC characteristics VDDA will never be reached as described in #362 and
/// [AN2834-How to get the best ADC accuracy in STM32 microcontrollers](https://www.st.com/resource/en/application_note/cd00211314-how-to-get-the-best-adc-accuracy-in-stm32-microcontrollers-stmicroelectronics.pdf) in section 3.1.2.
pub fn sample_to_millivolts(&self, sample: u16) -> u16 {
((u32::from(sample) * self.calibrated_vdda) / self.max_sample) as u16
}
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137 changes: 81 additions & 56 deletions src/sdio.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -339,12 +339,14 @@ impl Sdio {
self.cmd(cmd::read_single_block(blockaddr))?;

let mut i = 0;
let mut sta;

while {
sta = self.sdio.sta.read();
sta.rxact().bit_is_set()
} {
let status = loop {
let sta = self.sdio.sta.read();

if sta.rxact().bit_is_clear() {
break sta;
}

if sta.rxfifohf().bit() {
for _ in 0..8 {
let bytes = self.sdio.fifo.read().bits().to_le_bytes();
Expand All @@ -354,11 +356,11 @@ impl Sdio {
}

if i == block.len() {
break;
break sta;
}
}
};

status_to_error(sta)?;
status_to_error(status)?;

// Wait for card to be ready
while !self.card_ready()? {}
Expand All @@ -381,12 +383,14 @@ impl Sdio {
self.cmd(cmd::write_single_block(blockaddr))?;

let mut i = 0;
let mut sta;

while {
sta = self.sdio.sta.read();
sta.txact().bit_is_set()
} {
let status = loop {
let sta = self.sdio.sta.read();

if sta.txact().bit_is_clear() {
break sta;
}

if sta.txfifohe().bit() {
for _ in 0..8 {
let mut wb = [0u8; 4];
Expand All @@ -398,15 +402,15 @@ impl Sdio {
}

if i == block.len() {
break;
break sta;
}
}
};

status_to_error(sta)?;
status_to_error(status)?;

// Wait for SDIO module to finish transmitting data
loop {
sta = self.sdio.sta.read();
let sta = self.sdio.sta.read();
if !sta.txact().bit_is_set() {
break;
}
Expand All @@ -425,10 +429,16 @@ impl Sdio {
assert!(block_size <= 14);

// Command AND Data state machines must be idle
while self.sdio.sta.read().cmdact().bit_is_set()
|| self.sdio.sta.read().rxact().bit_is_set()
|| self.sdio.sta.read().txact().bit_is_set()
{}
loop {
let status = self.sdio.sta.read();

if status.cmdact().bit_is_clear()
&& status.rxact().bit_is_clear()
&& status.txact().bit_is_clear()
{
break;
}
}

let dtdir = if card_to_controller {
DTDIR_A::CARDTOCONTROLLER
Expand Down Expand Up @@ -475,12 +485,14 @@ impl Sdio {

let mut status = [0u32; 16];
let mut idx = 0;
let mut sta;

while {
sta = self.sdio.sta.read();
sta.rxact().bit_is_set()
} {
let s = loop {
let sta = self.sdio.sta.read();

if sta.rxact().bit_is_clear() {
break sta;
}

if sta.rxfifohf().bit() {
for _ in 0..8 {
status[15 - idx] = self.sdio.fifo.read().bits().swap_bytes();
Expand All @@ -489,11 +501,11 @@ impl Sdio {
}

if idx == status.len() {
break;
break sta;
}
}
};

status_to_error(sta)?;
status_to_error(s)?;
Ok(SDStatus::from(status))
}

Expand All @@ -515,23 +527,25 @@ impl Sdio {

let mut buf = [0; 2];
let mut i = 0;
let mut sta;

while {
sta = self.sdio.sta.read();
sta.rxact().bit_is_set()
} {
let status = loop {
let sta = self.sdio.sta.read();

if sta.rxact().bit_is_clear() {
break sta;
}

if sta.rxdavl().bit() {
buf[1 - i] = self.sdio.fifo.read().bits().swap_bytes();
i += 1;
}

if i == 2 {
break;
break sta;
}
}
};

status_to_error(sta)?;
status_to_error(status)?;
Ok(SCR::from(buf))
}

Expand Down Expand Up @@ -599,33 +613,44 @@ impl Sdio {

let mut timeout: u32 = 0xFFFF_FFFF;

let mut sta;
if cmd.response_len() == ResponseLen::Zero {
let status = if cmd.response_len() == ResponseLen::Zero {
// Wait for command sent or a timeout
while {
sta = self.sdio.sta.read();
loop {
let sta = self.sdio.sta.read();

if sta.cmdact().bit_is_clear()
&& (sta.ctimeout().bit_is_set() || sta.cmdsent().bit_is_set())
{
break sta;
}

if timeout == 0 {
return Err(Error::SoftwareTimeout);
}

(!(sta.ctimeout().bit() || sta.cmdsent().bit()) || sta.cmdact().bit_is_set())
&& timeout > 0
} {
timeout -= 1;
}
} else {
while {
sta = self.sdio.sta.read();
(!(sta.ctimeout().bit() || sta.cmdrend().bit() || sta.ccrcfail().bit())
|| sta.cmdact().bit_is_set())
&& timeout > 0
} {
loop {
let sta = self.sdio.sta.read();

if sta.cmdact().bit_is_clear()
&& (sta.ctimeout().bit()
|| sta.cmdrend().bit_is_set()
|| sta.ccrcfail().bit_is_set())
{
break sta;
}

if timeout == 0 {
return Err(Error::SoftwareTimeout);
}

timeout -= 1;
}
}

if timeout == 0 {
return Err(Error::SoftwareTimeout);
}
};

status_to_error(sta)
status_to_error(status)
}
}

Expand Down

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