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PWM: start_pwm resets ARPE bit in counter control register #501

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TorstenStrunk opened this issue Jul 4, 2022 · 1 comment
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PWM: start_pwm resets ARPE bit in counter control register #501

TorstenStrunk opened this issue Jul 4, 2022 · 1 comment

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@TorstenStrunk
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While using PWM output with different periods and duty cycles I observed glitches in the generated output signals. Even though the pwm and pwm_hz methods first enable auto reload preloads in CR1, the final call of self.tim.start_pwm() uses a write to CR1, which clears the ARPE bit again!
TorstenStrunk added a commit to TorstenStrunk/stm32f4xx-hal that referenced this issue Aug 13, 2022
@TorstenStrunk
Addressing issue stm32-rs#501 with start_pwm
43b4ab8 
Use register.modify instead of register.write method to start timer
(i.e. do same like calling timer.enable_counter()).
This avoids touching bits like ARPE (or DIR,..) which may have been set before
and should stay intact.
TorstenStrunk added a commit to TorstenStrunk/stm32f4xx-hal that referenced this issue Aug 13, 2022
@TorstenStrunk
Addressing issue stm32-rs#501 with start_pwm
e999df9 
Use register.modify instead of register.write method to start timer
(i.e. do same like calling timer.enable_counter()).
This avoids touching bits like ARPE (or DIR,..) which may have been set before
and should stay intact.
@TorstenStrunk TorstenStrunk mentioned this issue Aug 13, 2022
Merged
bors bot added a commit that referenced this issue Aug 14, 2022
@bors @TorstenStrunk
Merge #513
0db12eb 
513: Addressing issue #501 with start_pwm r=burrbull a=ganzalt

Second try to get issue #501 fixed.

Co-authored-by: ganzalt <torsten.strunk@gmx.de>
@TorstenStrunk
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This has been solved with #513

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@TorstenStrunk