The serial::Rx and uart::Rx splitting causes copypaste for high orger API

[qwerty19106]

@burrbull
The serial and uart was splitted in #608.

I read bytes by DMA until IDLE interrupt was received. I create support struct to reduce copypaste:

pub struct RxDmaIdle<STREAM, const CHANNEL: u8, USART, const BUFFER_SIZE: usize>
where
    STREAM: Stream,
    USART: Instance,
    Rx<USART>: PeriAddress<MemSize = u8>,
{
    transfer: Transfer<STREAM, CHANNEL, Rx<USART>, PeripheralToMemory, RxBufferObject<BUFFER_SIZE>>,
    pool: &'static ObjectPool<Vec<u8, BUFFER_SIZE>>,
}

impl<STREAM, const CHANNEL: u8, USART, const BUFFER_SIZE: usize>
    RxDmaIdle<STREAM, CHANNEL, USART, BUFFER_SIZE>
where
    STREAM: Stream,
    ChannelX<CHANNEL>: Channel,
    USART: Instance,
    Rx<USART>: PeriAddress<MemSize = u8> + RxISR + DMASet<STREAM, CHANNEL, PeripheralToMemory>,
    ...
{
	pub fn new(
        mut rx: Rx<USART>,
        stream: STREAM,
		...)  -> Self {
			rx.unlisten();
        	rx.listen_idle();	

			...
		}

	pub fn uart_interrupt_impl(
        &mut self,
    ) -> Result<RxBufferObject<BUFFER_SIZE>, RxPoolExhaustedError> {
		...
	}
}

But after #608 I should duplicate it for serial::Rx and uart::Rx because the unlisten() and listen_idle() is methods of Rx, not trait.

It would be logical to have one struct Rx for USART and UART, some common traits with common/different implementation and different traits with different implementation.
The Tx have the same problem.

Are there really important reasons to split serial::Rx and uart::Rx?

Full RxDmaIdle code

```Rust use embedded_dma::WriteBuffer; use heapless::{pool::object_simple::*, Vec}; use stm32f4xx_hal::{ dma::{ config::DmaConfig, traits::{Channel, DMASet, PeriAddress, Stream}, ChannelX, PeripheralToMemory, Transfer, }, serial::{Instance, Rx, RxISR}, };

use crate::{RxBufferObject, RxPoolExhaustedError};

pub struct RxDmaIdle<STREAM, const CHANNEL: u8, USART, const BUFFER_SIZE: usize>
where
STREAM: Stream,
USART: Instance,
Rx: PeriAddress<MemSize = u8>,
{
transfer: Transfer<STREAM, CHANNEL, Rx, PeripheralToMemory, RxBufferObject<BUFFER_SIZE>>,
pool: &'static ObjectPool<Vec<u8, BUFFER_SIZE>>,
}

impl<STREAM, const CHANNEL: u8, USART, const BUFFER_SIZE: usize>
RxDmaIdle<STREAM, CHANNEL, USART, BUFFER_SIZE>
where
STREAM: Stream,
ChannelX: Channel,
USART: Instance,
Rx: PeriAddress<MemSize = u8> + RxISR + DMASet<STREAM, CHANNEL, PeripheralToMemory>,
Object<Vec<u8, BUFFER_SIZE>>: WriteBuffer<Word = <Rx as PeriAddress>::MemSize>,
{
pub fn new(
mut rx: Rx,
stream: STREAM,
pool: &'static ObjectPool<Vec<u8, BUFFER_SIZE>>,
start: bool,
) -> Self {
rx.unlisten();
rx.listen_idle();

    let buffer = pool.request().unwrap();

    let mut transfer = Transfer::init_peripheral_to_memory(
        stream,
        rx,
        buffer,
        None,
        DmaConfig::default().memory_increment(true),
    );

    if start {
        transfer.start(|_| {});
    }

    Self { transfer, pool }
}

pub fn uart_interrupt_impl(
    &mut self,
) -> Result<RxBufferObject<BUFFER_SIZE>, RxPoolExhaustedError> {
    assert!(self.transfer.is_idle());

    self.transfer.clear_idle_interrupt();

    if let Some(next_buffer) = self.pool.request() {
        let number_of_transfers = STREAM::get_number_of_transfers() as usize;
        let bytes_count = BUFFER_SIZE - number_of_transfers;

        let (mut buffer, _) = self.transfer.next_transfer(next_buffer).unwrap();

        unsafe {
            buffer.set_len(bytes_count);
        }

        Ok(buffer)
    } else {
        Err(RxPoolExhaustedError)
    }
}

}

</details>

[burrbull]

It would be logical to have one struct Rx for USART and UART, some common traits with common/different implementation and different traits with different implementation.

I could not find how to leave these structures common between UART & USART with different RegisterBlocks.
If you have such solution I'm happy to look at it.
#608 is prep step for advanced possibilities different between UART and USART. For example #466. Although it is still blocked by stm32-rs release.
Technically the problem is missing specialization in Rust. When I try to do impl<U: I1> for Rx<U> { fn foo() } and impl<U: I2> for Rx<U> { fn foo() } Rust says about conflicting implementations. https://play.rust-lang.org/?version=stable&mode=debug&edition=2021&gist=5b2fb49cdad7745139d6fdd1a00669c7

About your idea about Listen trait. It is good to have such universal trait between different peripherals. Not only serial.

[qwerty19106]

Fixed on #636