Prevent overflows optimizing SAI PLL #419
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Add to changelog, please. |
burrbull
previously approved these changes
Jan 16, 2022
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rustfmt & squash |
Setting the common target PLL freq of 49.152MHz for the SAI clock (192kHz * 256) results in an overflow during multiplication. This patch catches the overflow, though I'm sure there's a better approach to optimizing the PLL settings that could avoid this.
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burrbull
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Jan 17, 2022
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bors r+ |
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Setting the common target PLL freq of 49.152 MHz for the SAI clock (192kHz * 256) results in an overflow during multiplication. This patch catches the overflow, though I'm sure there's a better approach to optimizing the PLL settings that could avoid this.