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Implement embedded-storage traits #429

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Feb 3, 2022
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chemicstry
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This PR implements embedded-storage traits for flash.

One major headache with F4 series is dual-bank flash and non-uniform sector sizes, which required quite a bit of code to abstract away. I went through all of the F4 reference manuals and believe that flash_sectors(...) function should be correct for all variants. AFAIK, there is no single source about flash layout for all the chips. Moreover, ST lists F429 and F469 with 512 KB of flash as dual-bank, but there is no information about it in the reference manual. I believe this could be an error in the website and only 1 MB chips have dual-bank capabilities.

The PAC crate is also missing DB1M field for some of the dual-bank capable chips, so for now I hardcoded the bit position in OPTCR register.

The writable NorFlash trait was implemented for the largest sector size of 128 KB, because embedded-storage does not intend to supprot non-uniform sectors (see comment). Smaller sectors are erased together in the larger 128 KB group. There was a suggestion to add different types for the smaller sector ranges, but I'm not sure if that is useful?

@burrbull
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burrbull commented Feb 3, 2022

LGTM. Could you add example? Or link on example in other repository to docs of flash.rs mod

@chemicstry
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Adding an example is problematic, because that requires modifying linker script to add an exclusive memory region for flash writing/reading and it has to not interfere with firmware binary size as well as total flash size. It would not be possible to have a single linker script that also supports 64K devices.

What if instead I added an inline example in the docs?

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burrbull commented Feb 3, 2022

bors r+

@bors bors bot merged commit 6613316 into stm32-rs:master Feb 3, 2022
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2 participants