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split master/slave spi structures #609
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Before this modification, I can use #![no_std]
#![no_main]
use panic_rtt_target as _;
use stm32f4xx_hal::{gpio::PinState, hal, pac, prelude::*};
#[cortex_m_rt::entry]
fn main() -> ! {
let dp = pac::Peripherals::take().unwrap();
let rcc = dp.RCC.constrain();
let clocks = rcc.cfgr.freeze();
let gpioa = dp.GPIOA.split();
// avoid random signal after release SPI
let sck_pin = gpioa.pa5.into_push_pull_output_in_state(PinState::High);
let miso_pin = gpioa.pa6.into_pull_down_input();
let mosi_pin = gpioa.pa7.into_push_pull_output_in_state(PinState::Low);
// assemble a SPI
dp.SPI1.spi(
(sck_pin, miso_pin, mosi_pin), // ERROR: trait bound not satisfied
hal::spi::MODE_0,
1.MHz(),
&clocks,
);
loop {}
} If I try do the same thing after this modification, I get some errors as such:
|
After 2 changes I suggest above, I can confirm it can run SPI Slave Mode successfully on my STM32F411RET6. |
This change was done before this PR. Anyway output/input modes are not correct modes for SPI for F4 serie (unlike F1). Correct modes are Previously there was hack for setting pins in alternate mode internally and restore on release without changing type. let (sck, miso, mosi) = spi.release();
let sck: PA5<Output> = sck.try_into()?;
... I could make possible to pass pin in any state although it is often misoptimize. let sck_pin = gpioa.pa5.internal_pull_up(true);
let miso_pin = gpioa.pa6.internal_pull_down(true);
let mosi_pin = gpioa.pa7.internal_pull_down(true);
// assemble a SPI
dp.SPI1.spi((sck_pin, miso_pin, mosi_pin) |
thanks, I didn't realize it's a hacky way to store pin state inside the |
you misunderstood me. I just said there has been a hack in code of hal to hide mode conversion from you. P.S. This PR #610 allows to pass pins in output mode. Although I still don't think this is good way to use output here. |
oh, sorry for my bad english, now I understand what you are talking about. |
Rebased on #610 |
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Merging this |
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