stm32-rs · burrbull · Nov 7, 2024 · Nov 7, 2024
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Bump `stm32f4-staging`
+
 ## [v0.22.1] - 2024-11-03
 
  - Fix pac `defmt` feature

diff --git a/Cargo.toml b/Cargo.toml
@@ -67,7 +67,7 @@ micromath = { version = "2.1.0", optional = true }
 
 [dependencies.stm32f4]
 package = "stm32f4-staging"
-version = "0.16.1"
+version = "0.17.0"
 features = ["atomics"]
 
 [dependencies.time]

diff --git a/src/adc.rs b/src/adc.rs
@@ -484,7 +484,7 @@ macro_rules! adc {
                         config::Sequence::Fourteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq14().bits(channel) }),
                         config::Sequence::Fifteen  => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq15().bits(channel) }),
                         config::Sequence::Sixteen  => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq16().bits(channel) }),
-                    }
+                    };
 
                     fn replace_bits(mut v: u32, offset: u32, width: u32, value: u32) -> u32 {
                         let mask = !(((1 << width) -1) << (offset * width));
@@ -500,7 +500,7 @@ macro_rules! adc {
                         0..=9   => self.adc_reg.smpr2().modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch, 3, st)) }),
                         10..=18 => self.adc_reg.smpr1().modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch-10, 3, st)) }),
                         _ => unimplemented!(),
-                    }
+                    };
                 }
 
                 /// Returns the current sample stored in the ADC data register

diff --git a/src/dsi.rs b/src/dsi.rs
@@ -387,7 +387,7 @@ impl DsiHost {
                     .modify(|_, w| unsafe { w.cmdsize().bits(display_config.active_width) });
 
                 // Tearing effect acknowledge request
-                dsi.cmcr().modify(|_, w| w.teare().set_bit())
+                dsi.cmcr().modify(|_, w| w.teare().set_bit());
             }
         }
 

diff --git a/src/fsmc_lcd/mod.rs b/src/fsmc_lcd/mod.rs
@@ -302,7 +302,7 @@ fn configure_bcr1<WORD: Word>(bcr: &fsmc::BCR1) {
         w.muxen().disabled();
         // Enable this memory bank
         w.mbken().enabled()
-    })
+    });
 }
 
 /// Configures an SRAM/NOR-Flash chip-select control register for LCD interface use
@@ -354,7 +354,7 @@ fn configure_bcr(bcr: &fsmc::BCR) {
             // Enable this memory bank
             .mbken()
             .enabled()
-    })
+    });
 }
 
 /// Configures a read timing register
@@ -370,7 +370,7 @@ fn configure_btr(btr: &fsmc::BTR, read_timing: &Timing) {
             .bits(read_timing.address_hold)
             .addset()
             .bits(read_timing.address_setup)
-    })
+    });
 }
 /// Configures a write timing register
 fn configure_bwtr(bwtr: &fsmc::BWTR, write_timing: &Timing) {
@@ -385,7 +385,7 @@ fn configure_bwtr(bwtr: &fsmc::BWTR, write_timing: &Timing) {
             .bits(write_timing.address_hold)
             .addset()
             .bits(write_timing.address_setup)
-    })
+    });
 }
 
 /// An interface to an LCD controller using one sub-bank

diff --git a/src/gpio.rs b/src/gpio.rs
@@ -450,13 +450,13 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
     fn _set_high(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
         let gpio = unsafe { &(*gpiox::<P>()) };
-        gpio.bsrr().write(|w| w.bs(N).set_bit())
+        gpio.bsrr().write(|w| w.bs(N).set_bit());
     }
     #[inline(always)]
     fn _set_low(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
         let gpio = unsafe { &(*gpiox::<P>()) };
-        gpio.bsrr().write(|w| w.br(N).set_bit())
+        gpio.bsrr().write(|w| w.br(N).set_bit());
     }
     #[inline(always)]
     fn _is_set_low(&self) -> bool {

diff --git a/src/gpio/outport.rs b/src/gpio/outport.rs
@@ -31,17 +31,17 @@ macro_rules! out_port {
             #[doc=concat!("Set/reset pins according to `", $n, "` lower bits")]
             #[inline(never)]
             pub fn write(&mut self, word: u32) {
-                unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::value_for_write_bsrr(word))) }
+                unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::value_for_write_bsrr(word))); }
             }
 
             /// Set all pins to `PinState::High`
             pub fn all_high(&mut self) {
-                unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask())) }
+                unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask())); }
             }
 
             /// Reset all pins to `PinState::Low`
             pub fn all_low(&mut self) {
-                unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask() << 16)) }
+                unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask() << 16)); }
             }
         }
     }
@@ -88,17 +88,21 @@ impl<const P: char, const SIZE: usize> OutPortArray<P, SIZE> {
         unsafe {
             (*gpiox::<P>())
                 .bsrr()
-                .write(|w| w.bits(self.value_for_write_bsrr(word)))
+                .write(|w| w.bits(self.value_for_write_bsrr(word)));
         }
     }
 
     /// Set all pins to `PinState::High`
     pub fn all_high(&mut self) {
-        unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask())) }
+        unsafe {
+            (*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask()));
+        }
     }
 
     /// Reset all pins to `PinState::Low`
     pub fn all_low(&mut self) {
-        unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask() << 16)) }
+        unsafe {
+            (*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask() << 16));
+        }
     }
 }
diff --git a/src/gpio/partially_erased.rs b/src/gpio/partially_erased.rs
@@ -68,14 +68,18 @@ impl<const P: char, MODE> PartiallyErasedPin<P, Output<MODE>> {
     #[inline(always)]
     pub fn set_high(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
-        unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(1 << self.i)) }
+        unsafe {
+            (*gpiox::<P>()).bsrr().write(|w| w.bits(1 << self.i));
+        }
     }
 
     /// Drives the pin low
     #[inline(always)]
     pub fn set_low(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
-        unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(1 << (self.i + 16))) }
+        unsafe {
+            (*gpiox::<P>()).bsrr().write(|w| w.bits(1 << (self.i + 16)));
+        }
     }
 
     /// Is the pin in drive high or low mode?

diff --git a/src/rcc/f4/mod.rs b/src/rcc/f4/mod.rs
@@ -526,7 +526,7 @@ impl CFGR {
                 w.prften().set_bit();
                 w.icen().set_bit();
                 w.dcen().set_bit()
-            })
+            });
         }
     }
 

diff --git a/src/rtc.rs b/src/rtc.rs
@@ -183,7 +183,7 @@ impl Rtc {
             regs.prer().modify(|_, w| {
                 w.prediv_s().set(prediv_s);
                 w.prediv_a().set(prediv_a)
-            })
+            });
         });
 
         result
@@ -261,7 +261,7 @@ impl Rtc {
             regs.prer().modify(|_, w| {
                 w.prediv_s().set(prediv_s);
                 w.prediv_a().set(prediv_a)
-            })
+            });
         });
     }
 
@@ -311,7 +311,7 @@ impl Rtc {
                 w.st().set(st);
                 w.su().set(su);
                 w.pm().clear_bit()
-            })
+            });
         });
 
         Ok(())
@@ -324,7 +324,7 @@ impl Rtc {
         }
         let (st, su) = bcd2_encode(seconds.into())?;
         self.modify(true, |regs| {
-            regs.tr().modify(|_, w| w.st().set(st).su().set(su))
+            regs.tr().modify(|_, w| w.st().set(st).su().set(su));
         });
 
         Ok(())
@@ -337,7 +337,7 @@ impl Rtc {
         }
         let (mnt, mnu) = bcd2_encode(minutes.into())?;
         self.modify(true, |regs| {
-            regs.tr().modify(|_, w| w.mnt().set(mnt).mnu().set(mnu))
+            regs.tr().modify(|_, w| w.mnt().set(mnt).mnu().set(mnu));
         });
 
         Ok(())
@@ -351,7 +351,7 @@ impl Rtc {
         let (ht, hu) = bcd2_encode(hours.into())?;
 
         self.modify(true, |regs| {
-            regs.tr().modify(|_, w| w.ht().set(ht).hu().set(hu))
+            regs.tr().modify(|_, w| w.ht().set(ht).hu().set(hu));
         });
 
         Ok(())
@@ -363,7 +363,7 @@ impl Rtc {
             return Err(Error::InvalidInputData);
         }
         self.modify(true, |regs| {
-            regs.dr().modify(|_, w| unsafe { w.wdu().bits(weekday) })
+            regs.dr().modify(|_, w| unsafe { w.wdu().bits(weekday) });
         });
 
         Ok(())
@@ -376,7 +376,7 @@ impl Rtc {
         }
         let (dt, du) = bcd2_encode(day as u32)?;
         self.modify(true, |regs| {
-            regs.dr().modify(|_, w| w.dt().set(dt).du().set(du))
+            regs.dr().modify(|_, w| w.dt().set(dt).du().set(du));
         });
 
         Ok(())
@@ -389,7 +389,7 @@ impl Rtc {
         }
         let (mt, mu) = bcd2_encode(month as u32)?;
         self.modify(true, |regs| {
-            regs.dr().modify(|_, w| w.mt().bit(mt > 0).mu().set(mu))
+            regs.dr().modify(|_, w| w.mt().bit(mt > 0).mu().set(mu));
         });
 
         Ok(())
@@ -405,7 +405,7 @@ impl Rtc {
         }
         let (yt, yu) = bcd2_encode(year as u32 - 1970)?;
         self.modify(true, |regs| {
-            regs.dr().modify(|_, w| w.yt().set(yt).yu().set(yu))
+            regs.dr().modify(|_, w| w.yt().set(yt).yu().set(yu));
         });
 
         Ok(())
@@ -434,7 +434,7 @@ impl Rtc {
                 w.yt().set(yt);
                 w.yu().set(yu);
                 unsafe { w.wdu().bits(wdu) }
-            })
+            });
         });
 
         Ok(())
@@ -476,7 +476,7 @@ impl Rtc {
                 w.st().set(st);
                 w.su().set(su);
                 w.pm().clear_bit()
-            })
+            });
         });
 
         Ok(())

diff --git a/src/serial/uart_impls.rs b/src/serial/uart_impls.rs
@@ -267,9 +267,15 @@ macro_rules! uartCommon {
         fn enable_dma(&self, dc: config::DmaConfig) {
             use config::DmaConfig;
             match dc {
-                DmaConfig::Tx => self.cr3().write(|w| w.dmat().enabled()),
-                DmaConfig::Rx => self.cr3().write(|w| w.dmar().enabled()),
-                DmaConfig::TxRx => self.cr3().write(|w| w.dmar().enabled().dmat().enabled()),
+                DmaConfig::Tx => {
+                    self.cr3().write(|w| w.dmat().enabled());
+                }
+                DmaConfig::Rx => {
+                    self.cr3().write(|w| w.dmar().enabled());
+                }
+                DmaConfig::TxRx => {
+                    self.cr3().write(|w| w.dmar().enabled().dmat().enabled());
+                }
                 DmaConfig::None => {}
             }
         }
@@ -369,14 +375,14 @@ where {
             IrdaMode::Normal => unsafe {
                 uart.gtpr().reset();
                 uart.cr3().write(|w| w.iren().enabled());
-                uart.gtpr().write(|w| w.psc().bits(1u8))
+                uart.gtpr().write(|w| w.psc().bits(1u8));
             },
             IrdaMode::LowPower => unsafe {
                 uart.gtpr().reset();
                 uart.cr3().write(|w| w.iren().enabled().irlp().low_power());
                 // FIXME
                 uart.gtpr()
-                    .write(|w| w.psc().bits((1843200u32 / pclk_freq) as u8))
+                    .write(|w| w.psc().bits((1843200u32 / pclk_freq) as u8));
             },
             IrdaMode::None => {}
         }

diff --git a/src/spi.rs b/src/spi.rs
@@ -139,7 +139,7 @@ impl FrameSize for u8 {
         spi.dr8().read().dr().bits()
     }
     fn write_data(self, spi: &spi1::RegisterBlock) {
-        spi.dr8().write(|w| w.dr().set(self))
+        spi.dr8().write(|w| w.dr().set(self));
     }
 }
 
@@ -149,7 +149,7 @@ impl FrameSize for u16 {
         spi.dr().read().dr().bits()
     }
     fn write_data(self, spi: &spi1::RegisterBlock) {
-        spi.dr().write(|w| w.dr().set(self))
+        spi.dr().write(|w| w.dr().set(self));
     }
 }
 
@@ -868,7 +868,7 @@ impl<SPI: Instance> crate::ClearFlags for Inner<SPI> {
         if flags.into().contains(CFlag::CrcError) {
             self.spi
                 .sr()
-                .write(|w| unsafe { w.bits(0xffff).crcerr().clear_bit() })
+                .write(|w| unsafe { w.bits(0xffff).crcerr().clear_bit() });
         }
     }
 }

diff --git a/src/timer.rs b/src/timer.rs
@@ -436,7 +436,7 @@ macro_rules! hal {
             }
             #[inline(always)]
             unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {
-                self.arr().write(|w| w.bits(arr))
+                self.arr().write(|w| w.bits(arr));
             }
             #[inline(always)]
             fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {
@@ -551,7 +551,7 @@ macro_rules! hal {
                 fn set_cc_value(c: u8, value: u32) {
                     let tim = unsafe { &*<$TIM>::ptr() };
                     if c < Self::CH_NUMBER {
-                        tim.ccr(c as usize).write(|w| unsafe { w.bits(value) })
+                        tim.ccr(c as usize).write(|w| unsafe { w.bits(value) });
                     }
                 }